1 /* 2 * Copyright (c) 2021 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 /* 7 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 8 * 9 * Functions here are designed to produce efficient code to 10 * search an Xtensa bitmask of interrupts, inspecting only those bits 11 * declared to be associated with a given interrupt level. Each 12 * dispatcher will handle exactly one flagged interrupt, in numerical 13 * order (low bits first) and will return a mask of that bit that can 14 * then be cleared by the calling code. Unrecognized bits for the 15 * level will invoke an error handler. 16 */ 17 18 #include <xtensa/config/core-isa.h> 19 #include <zephyr/sys/util.h> 20 #include <zephyr/sw_isr_table.h> 21 22 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5 23 #error core-isa.h interrupt level does not match dispatcher! 24 #endif 25 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3 26 #error core-isa.h interrupt level does not match dispatcher! 27 #endif 28 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2 29 #error core-isa.h interrupt level does not match dispatcher! 30 #endif 31 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3 32 #error core-isa.h interrupt level does not match dispatcher! 33 #endif 34 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2 35 #error core-isa.h interrupt level does not match dispatcher! 36 #endif 37 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2 38 #error core-isa.h interrupt level does not match dispatcher! 39 #endif 40 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2 41 #error core-isa.h interrupt level does not match dispatcher! 42 #endif 43 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2 44 #error core-isa.h interrupt level does not match dispatcher! 45 #endif 46 #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 47 #error core-isa.h interrupt level does not match dispatcher! 48 #endif 49 #if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2 50 #error core-isa.h interrupt level does not match dispatcher! 51 #endif 52 #if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2 53 #error core-isa.h interrupt level does not match dispatcher! 54 #endif 55 #if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2 56 #error core-isa.h interrupt level does not match dispatcher! 57 #endif 58 #if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2 59 #error core-isa.h interrupt level does not match dispatcher! 60 #endif 61 #if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2 62 #error core-isa.h interrupt level does not match dispatcher! 63 #endif 64 #if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2 65 #error core-isa.h interrupt level does not match dispatcher! 66 #endif 67 #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2 68 #error core-isa.h interrupt level does not match dispatcher! 69 #endif 70 #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2 71 #error core-isa.h interrupt level does not match dispatcher! 72 #endif 73 #if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2 74 #error core-isa.h interrupt level does not match dispatcher! 75 #endif 76 #if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2 77 #error core-isa.h interrupt level does not match dispatcher! 78 #endif 79 #if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 80 #error core-isa.h interrupt level does not match dispatcher! 81 #endif 82 #if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 83 #error core-isa.h interrupt level does not match dispatcher! 84 #endif 85 _xtensa_handle_one_int1(unsigned int mask)86static inline int _xtensa_handle_one_int1(unsigned int mask) 87 { 88 int irq; 89 90 if (mask & BIT(8)) { 91 mask = BIT(8); 92 irq = 8; 93 goto handle_irq; 94 } 95 return 0; 96 handle_irq: 97 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 98 return mask; 99 } 100 _xtensa_handle_one_int2(unsigned int mask)101static inline int _xtensa_handle_one_int2(unsigned int mask) 102 { 103 int irq; 104 int i = 0; 105 106 mask &= XCHAL_INTLEVEL2_MASK; 107 for (i = 0; i <= 31; i++) { 108 if (mask & BIT(i)) { 109 mask = BIT(i); 110 irq = i; 111 goto handle_irq; 112 } 113 } 114 return 0; 115 handle_irq: 116 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 117 return mask; 118 } 119 _xtensa_handle_one_int3(unsigned int mask)120static inline int _xtensa_handle_one_int3(unsigned int mask) 121 { 122 int irq; 123 124 if (mask & BIT(1)) { 125 mask = BIT(1); 126 irq = 1; 127 goto handle_irq; 128 } 129 if (mask & BIT(3)) { 130 mask = BIT(3); 131 irq = 3; 132 goto handle_irq; 133 } 134 if (mask & BIT(31)) { 135 mask = BIT(31); 136 irq = 31; 137 goto handle_irq; 138 } 139 return 0; 140 handle_irq: 141 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 142 return mask; 143 } 144 _xtensa_handle_one_int5(unsigned int mask)145static inline int _xtensa_handle_one_int5(unsigned int mask) 146 { 147 int irq; 148 149 if (mask & BIT(0)) { 150 mask = BIT(0); 151 irq = 0; 152 goto handle_irq; 153 } 154 return 0; 155 handle_irq: 156 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 157 return mask; 158 } 159 _xtensa_handle_one_int0(unsigned int mask)160static inline int _xtensa_handle_one_int0(unsigned int mask) 161 { 162 return 0; 163 } 164 _xtensa_handle_one_int4(unsigned int mask)165static inline int _xtensa_handle_one_int4(unsigned int mask) 166 { 167 return 0; 168 } 169 _xtensa_handle_one_int6(unsigned int mask)170static inline int _xtensa_handle_one_int6(unsigned int mask) 171 { 172 return 0; 173 } 174 _xtensa_handle_one_int7(unsigned int mask)175static inline int _xtensa_handle_one_int7(unsigned int mask) 176 { 177 return 0; 178 } 179
