1 /* 2 * Copyright (c) 2023 Google LLC. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #include <xtensa/config/core-isa.h> 7 #include <zephyr/sys/util.h> 8 #include <zephyr/sw_isr_table.h> 9 10 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5 11 #error core-isa.h interrupt level does not match dispatcher! 12 #endif 13 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 2 14 #error core-isa.h interrupt level does not match dispatcher! 15 #endif 16 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2 17 #error core-isa.h interrupt level does not match dispatcher! 18 #endif 19 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3 20 #error core-isa.h interrupt level does not match dispatcher! 21 #endif 22 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 3 23 #error core-isa.h interrupt level does not match dispatcher! 24 #endif 25 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 26 #error core-isa.h interrupt level does not match dispatcher! 27 #endif 28 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 29 #error core-isa.h interrupt level does not match dispatcher! 30 #endif 31 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 32 #error core-isa.h interrupt level does not match dispatcher! 33 #endif 34 #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 35 #error core-isa.h interrupt level does not match dispatcher! 36 #endif 37 #if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 38 #error core-isa.h interrupt level does not match dispatcher! 39 #endif 40 #if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 41 #error core-isa.h interrupt level does not match dispatcher! 42 #endif 43 #if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 1 44 #error core-isa.h interrupt level does not match dispatcher! 45 #endif 46 #if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 47 #error core-isa.h interrupt level does not match dispatcher! 48 #endif 49 #if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 50 #error core-isa.h interrupt level does not match dispatcher! 51 #endif 52 #if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 1 53 #error core-isa.h interrupt level does not match dispatcher! 54 #endif 55 #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1 56 #error core-isa.h interrupt level does not match dispatcher! 57 #endif 58 #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2 59 #error core-isa.h interrupt level does not match dispatcher! 60 #endif 61 #if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2 62 #error core-isa.h interrupt level does not match dispatcher! 63 #endif 64 #if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2 65 #error core-isa.h interrupt level does not match dispatcher! 66 #endif 67 #if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 68 #error core-isa.h interrupt level does not match dispatcher! 69 #endif 70 #if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 71 #error core-isa.h interrupt level does not match dispatcher! 72 #endif 73 #if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 74 #error core-isa.h interrupt level does not match dispatcher! 75 #endif 76 #if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 2 77 #error core-isa.h interrupt level does not match dispatcher! 78 #endif 79 #if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 2 80 #error core-isa.h interrupt level does not match dispatcher! 81 #endif 82 #if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 3 83 #error core-isa.h interrupt level does not match dispatcher! 84 #endif 85 #if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 3 86 #error core-isa.h interrupt level does not match dispatcher! 87 #endif 88 #if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 3 89 #error core-isa.h interrupt level does not match dispatcher! 90 #endif 91 #if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 92 #error core-isa.h interrupt level does not match dispatcher! 93 #endif 94 #if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 3 95 #error core-isa.h interrupt level does not match dispatcher! 96 #endif 97 #if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 98 #error core-isa.h interrupt level does not match dispatcher! 99 #endif 100 #if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 3 101 #error core-isa.h interrupt level does not match dispatcher! 102 #endif 103 #if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 3 104 #error core-isa.h interrupt level does not match dispatcher! 105 #endif 106 107 /* 108 * Interrupt masks for every level (RT595 ADSP): 109 * XCHAL_INTLEVEL1_MASK: 0x0000FFE0 110 * XCHAL_INTLEVEL2_MASK: 0x00FF0006 111 * XCHAL_INTLEVEL3_MASK: 0xFF000018 112 * XCHAL_INTLEVEL4_MASK: 0x00000000 113 * XCHAL_INTLEVEL5_MASK: 0x00000001 114 */ 115 _xtensa_handle_one_int1(unsigned int mask)116static inline int _xtensa_handle_one_int1(unsigned int mask) 117 { 118 int irq; 119 120 mask &= XCHAL_INTLEVEL1_MASK; 121 for (int i = 5; i <= 31; i++) { 122 if (mask & BIT(i)) { 123 mask = BIT(i); 124 irq = i; 125 goto handle_irq; 126 } 127 } 128 return 0; 129 handle_irq: 130 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 131 return mask; 132 } 133 _xtensa_handle_one_int2(unsigned int mask)134static inline int _xtensa_handle_one_int2(unsigned int mask) 135 { 136 int irq; 137 138 mask &= XCHAL_INTLEVEL2_MASK; 139 for (int i = 1; i <= 31; i++) { 140 if (mask & BIT(i)) { 141 mask = BIT(i); 142 irq = i; 143 goto handle_irq; 144 } 145 } 146 return 0; 147 handle_irq: 148 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 149 return mask; 150 } 151 _xtensa_handle_one_int3(unsigned int mask)152static inline int _xtensa_handle_one_int3(unsigned int mask) 153 { 154 int irq; 155 156 mask &= XCHAL_INTLEVEL3_MASK; 157 for (int i = 3; i <= 31; i++) { 158 if (mask & BIT(i)) { 159 mask = BIT(i); 160 irq = i; 161 goto handle_irq; 162 } 163 } 164 return 0; 165 handle_irq: 166 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 167 return mask; 168 } 169 _xtensa_handle_one_int4(unsigned int mask)170static inline int _xtensa_handle_one_int4(unsigned int mask) 171 { 172 return 0; 173 } 174 _xtensa_handle_one_int5(unsigned int mask)175static inline int _xtensa_handle_one_int5(unsigned int mask) 176 { 177 int irq; 178 179 if (mask & BIT(0)) { 180 mask = BIT(0); 181 irq = 0; 182 goto handle_irq; 183 } 184 return 0; 185 handle_irq: 186 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 187 return mask; 188 } 189
