1 /* 2 * Copyright (c) 2024 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 9 * 10 * Functions here are designed to produce efficient code to 11 * search an Xtensa bitmask of interrupts, inspecting only those bits 12 * declared to be associated with a given interrupt level. Each 13 * dispatcher will handle exactly one flagged interrupt, in numerical 14 * order (low bits first) and will return a mask of that bit that can 15 * then be cleared by the calling code. Unrecognized bits for the 16 * level will invoke an error handler. 17 */ 18 19 #include <xtensa/config/core-isa.h> 20 #include <zephyr/sys/util.h> 21 #include <zephyr/sw_isr_table.h> 22 23 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 24 #error core-isa.h interrupt level does not match dispatcher! 25 #endif 26 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 27 #error core-isa.h interrupt level does not match dispatcher! 28 #endif 29 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 30 #error core-isa.h interrupt level does not match dispatcher! 31 #endif 32 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 33 #error core-isa.h interrupt level does not match dispatcher! 34 #endif 35 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 36 #error core-isa.h interrupt level does not match dispatcher! 37 #endif 38 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 39 #error core-isa.h interrupt level does not match dispatcher! 40 #endif 41 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 42 #error core-isa.h interrupt level does not match dispatcher! 43 #endif 44 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 45 #error core-isa.h interrupt level does not match dispatcher! 46 #endif 47 #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1 48 #error core-isa.h interrupt level does not match dispatcher! 49 #endif 50 #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 1 51 #error core-isa.h interrupt level does not match dispatcher! 52 #endif 53 #if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 54 #error core-isa.h interrupt level does not match dispatcher! 55 #endif 56 #if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 57 #error core-isa.h interrupt level does not match dispatcher! 58 #endif 59 #if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 1 60 #error core-isa.h interrupt level does not match dispatcher! 61 #endif 62 #if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 1 63 #error core-isa.h interrupt level does not match dispatcher! 64 #endif 65 #if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 1 66 #error core-isa.h interrupt level does not match dispatcher! 67 #endif 68 #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 2 69 #error core-isa.h interrupt level does not match dispatcher! 70 #endif 71 #if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3 72 #error core-isa.h interrupt level does not match dispatcher! 73 #endif 74 #if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3 75 #error core-isa.h interrupt level does not match dispatcher! 76 #endif 77 #if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 78 #error core-isa.h interrupt level does not match dispatcher! 79 #endif 80 #if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 3 81 #error core-isa.h interrupt level does not match dispatcher! 82 #endif 83 #if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4 84 #error core-isa.h interrupt level does not match dispatcher! 85 #endif 86 #if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 5 87 #error core-isa.h interrupt level does not match dispatcher! 88 #endif 89 #if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 90 #error core-isa.h interrupt level does not match dispatcher! 91 #endif 92 _xtensa_handle_one_int1(unsigned int mask)93static inline int _xtensa_handle_one_int1(unsigned int mask) 94 { 95 int irq; 96 97 if (mask & 0x7f) { 98 if (mask & 0x7) { 99 if (mask & BIT(0)) { 100 mask = BIT(0); 101 irq = 0; 102 goto handle_irq; 103 } 104 if (mask & BIT(1)) { 105 mask = BIT(1); 106 irq = 1; 107 goto handle_irq; 108 } 109 if (mask & BIT(2)) { 110 mask = BIT(2); 111 irq = 2; 112 goto handle_irq; 113 } 114 } else { 115 if (mask & 0x18) { 116 if (mask & BIT(3)) { 117 mask = BIT(3); 118 irq = 3; 119 goto handle_irq; 120 } 121 if (mask & BIT(4)) { 122 mask = BIT(4); 123 irq = 4; 124 goto handle_irq; 125 } 126 } else { 127 if (mask & BIT(5)) { 128 mask = BIT(5); 129 irq = 5; 130 goto handle_irq; 131 } 132 if (mask & BIT(6)) { 133 mask = BIT(6); 134 irq = 6; 135 goto handle_irq; 136 } 137 } 138 } 139 } else { 140 if (mask & 0x38080) { 141 if (mask & 0x8080) { 142 if (mask & BIT(7)) { 143 mask = BIT(7); 144 irq = 7; 145 goto handle_irq; 146 } 147 if (mask & BIT(15)) { 148 mask = BIT(15); 149 irq = 15; 150 goto handle_irq; 151 } 152 } else { 153 if (mask & BIT(16)) { 154 mask = BIT(16); 155 irq = 16; 156 goto handle_irq; 157 } 158 if (mask & BIT(17)) { 159 mask = BIT(17); 160 irq = 17; 161 goto handle_irq; 162 } 163 } 164 } else { 165 if (mask & 0xc0000) { 166 if (mask & BIT(18)) { 167 mask = BIT(18); 168 irq = 18; 169 goto handle_irq; 170 } 171 if (mask & BIT(19)) { 172 mask = BIT(19); 173 irq = 19; 174 goto handle_irq; 175 } 176 } else { 177 if (mask & BIT(20)) { 178 mask = BIT(20); 179 irq = 20; 180 goto handle_irq; 181 } 182 if (mask & BIT(22)) { 183 mask = BIT(22); 184 irq = 22; 185 goto handle_irq; 186 } 187 } 188 } 189 } 190 return 0; 191 handle_irq: 192 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 193 return mask; 194 } 195 _xtensa_handle_one_int2(unsigned int mask)196static inline int _xtensa_handle_one_int2(unsigned int mask) 197 { 198 int irq; 199 200 if (mask & BIT(8)) { 201 mask = BIT(8); 202 irq = 8; 203 goto handle_irq; 204 } 205 return 0; 206 handle_irq: 207 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 208 return mask; 209 } 210 _xtensa_handle_one_int3(unsigned int mask)211static inline int _xtensa_handle_one_int3(unsigned int mask) 212 { 213 int irq; 214 215 if (mask & 0x600) { 216 if (mask & BIT(9)) { 217 mask = BIT(9); 218 irq = 9; 219 goto handle_irq; 220 } 221 if (mask & BIT(10)) { 222 mask = BIT(10); 223 irq = 10; 224 goto handle_irq; 225 } 226 } else { 227 if (mask & BIT(11)) { 228 mask = BIT(11); 229 irq = 11; 230 goto handle_irq; 231 } 232 if (mask & BIT(21)) { 233 mask = BIT(21); 234 irq = 21; 235 goto handle_irq; 236 } 237 } 238 return 0; 239 handle_irq: 240 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 241 return mask; 242 } 243 _xtensa_handle_one_int4(unsigned int mask)244static inline int _xtensa_handle_one_int4(unsigned int mask) 245 { 246 int irq; 247 248 if (mask & BIT(12)) { 249 mask = BIT(12); 250 irq = 12; 251 goto handle_irq; 252 } 253 return 0; 254 handle_irq: 255 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 256 return mask; 257 } 258 _xtensa_handle_one_int5(unsigned int mask)259static inline int _xtensa_handle_one_int5(unsigned int mask) 260 { 261 int irq; 262 263 if (mask & BIT(13)) { 264 mask = BIT(13); 265 irq = 13; 266 goto handle_irq; 267 } 268 return 0; 269 handle_irq: 270 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 271 return mask; 272 } 273 _xtensa_handle_one_int7(unsigned int mask)274static inline int _xtensa_handle_one_int7(unsigned int mask) 275 { 276 int irq; 277 278 if (mask & BIT(14)) { 279 mask = BIT(14); 280 irq = 14; 281 goto handle_irq; 282 } 283 return 0; 284 handle_irq: 285 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 286 return mask; 287 } 288 _xtensa_handle_one_int0(unsigned int mask)289static inline int _xtensa_handle_one_int0(unsigned int mask) 290 { 291 return 0; 292 } _xtensa_handle_one_int6(unsigned int mask)293static inline int _xtensa_handle_one_int6(unsigned int mask) 294 { 295 return 0; 296 } 297
