1 /* 2 * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 9 * 10 * Functions here are designed to produce efficient code to 11 * search an Xtensa bitmask of interrupts, inspecting only those bits 12 * declared to be associated with a given interrupt level. Each 13 * dispatcher will handle exactly one flagged interrupt, in numerical 14 * order (low bits first) and will return a mask of that bit that can 15 * then be cleared by the calling code. Unrecognized bits for the 16 * level will invoke an error handler. 17 */ 18 19 #include <xtensa/config/core-isa.h> 20 #include <zephyr/sys/util.h> 21 #include <zephyr/sw_isr_table.h> 22 23 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 24 #error core-isa.h interrupt level does not match dispatcher! 25 #endif 26 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 27 #error core-isa.h interrupt level does not match dispatcher! 28 #endif 29 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 30 #error core-isa.h interrupt level does not match dispatcher! 31 #endif 32 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 33 #error core-isa.h interrupt level does not match dispatcher! 34 #endif 35 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 36 #error core-isa.h interrupt level does not match dispatcher! 37 #endif 38 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 39 #error core-isa.h interrupt level does not match dispatcher! 40 #endif 41 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 42 #error core-isa.h interrupt level does not match dispatcher! 43 #endif 44 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 45 #error core-isa.h interrupt level does not match dispatcher! 46 #endif 47 #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 48 #error core-isa.h interrupt level does not match dispatcher! 49 #endif 50 #if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 51 #error core-isa.h interrupt level does not match dispatcher! 52 #endif 53 #if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 54 #error core-isa.h interrupt level does not match dispatcher! 55 #endif 56 #if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 57 #error core-isa.h interrupt level does not match dispatcher! 58 #endif 59 #if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 60 #error core-isa.h interrupt level does not match dispatcher! 61 #endif 62 #if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 63 #error core-isa.h interrupt level does not match dispatcher! 64 #endif 65 #if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 66 #error core-isa.h interrupt level does not match dispatcher! 67 #endif 68 #if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 69 #error core-isa.h interrupt level does not match dispatcher! 70 #endif 71 #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3 72 #error core-isa.h interrupt level does not match dispatcher! 73 #endif 74 #if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3 75 #error core-isa.h interrupt level does not match dispatcher! 76 #endif 77 #if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3 78 #error core-isa.h interrupt level does not match dispatcher! 79 #endif 80 #if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 81 #error core-isa.h interrupt level does not match dispatcher! 82 #endif 83 #if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 84 #error core-isa.h interrupt level does not match dispatcher! 85 #endif 86 #if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 87 #error core-isa.h interrupt level does not match dispatcher! 88 #endif 89 #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 90 #error core-isa.h interrupt level does not match dispatcher! 91 #endif 92 #if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5 93 #error core-isa.h interrupt level does not match dispatcher! 94 #endif 95 #if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5 96 #error core-isa.h interrupt level does not match dispatcher! 97 #endif 98 #if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 99 #error core-isa.h interrupt level does not match dispatcher! 100 #endif 101 #if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 102 #error core-isa.h interrupt level does not match dispatcher! 103 #endif 104 #if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 105 #error core-isa.h interrupt level does not match dispatcher! 106 #endif 107 #if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4 108 #error core-isa.h interrupt level does not match dispatcher! 109 #endif 110 #if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4 111 #error core-isa.h interrupt level does not match dispatcher! 112 #endif 113 #if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4 114 #error core-isa.h interrupt level does not match dispatcher! 115 #endif 116 #if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4 117 #error core-isa.h interrupt level does not match dispatcher! 118 #endif 119 _xtensa_handle_one_int1(unsigned int mask)120static inline int _xtensa_handle_one_int1(unsigned int mask) 121 { 122 int irq; 123 124 if (mask & 0x7f) { 125 if (mask & 0x7) { 126 if (mask & BIT(0)) { 127 mask = BIT(0); 128 irq = 0; 129 goto handle_irq; 130 } 131 if (mask & BIT(1)) { 132 mask = BIT(1); 133 irq = 1; 134 goto handle_irq; 135 } 136 if (mask & BIT(2)) { 137 mask = BIT(2); 138 irq = 2; 139 goto handle_irq; 140 } 141 } else { 142 if (mask & 0x18) { 143 if (mask & BIT(3)) { 144 mask = BIT(3); 145 irq = 3; 146 goto handle_irq; 147 } 148 if (mask & BIT(4)) { 149 mask = BIT(4); 150 irq = 4; 151 goto handle_irq; 152 } 153 } else { 154 if (mask & BIT(5)) { 155 mask = BIT(5); 156 irq = 5; 157 goto handle_irq; 158 } 159 if (mask & BIT(6)) { 160 mask = BIT(6); 161 irq = 6; 162 goto handle_irq; 163 } 164 } 165 } 166 } else { 167 if (mask & 0x780) { 168 if (mask & 0x180) { 169 if (mask & BIT(7)) { 170 mask = BIT(7); 171 irq = 7; 172 goto handle_irq; 173 } 174 if (mask & BIT(8)) { 175 mask = BIT(8); 176 irq = 8; 177 goto handle_irq; 178 } 179 } else { 180 if (mask & BIT(9)) { 181 mask = BIT(9); 182 irq = 9; 183 goto handle_irq; 184 } 185 if (mask & BIT(10)) { 186 mask = BIT(10); 187 irq = 10; 188 goto handle_irq; 189 } 190 } 191 } else { 192 if (mask & 0x3000) { 193 if (mask & BIT(12)) { 194 mask = BIT(12); 195 irq = 12; 196 goto handle_irq; 197 } 198 if (mask & BIT(13)) { 199 mask = BIT(13); 200 irq = 13; 201 goto handle_irq; 202 } 203 } else { 204 if (mask & BIT(17)) { 205 mask = BIT(17); 206 irq = 17; 207 goto handle_irq; 208 } 209 if (mask & BIT(18)) { 210 mask = BIT(18); 211 irq = 18; 212 goto handle_irq; 213 } 214 } 215 } 216 } 217 return 0; 218 handle_irq: 219 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 220 return mask; 221 } 222 _xtensa_handle_one_int3(unsigned int mask)223static inline int _xtensa_handle_one_int3(unsigned int mask) 224 { 225 int irq; 226 227 if (mask & 0x408800) { 228 if (mask & BIT(11)) { 229 mask = BIT(11); 230 irq = 11; 231 goto handle_irq; 232 } 233 if (mask & BIT(15)) { 234 mask = BIT(15); 235 irq = 15; 236 goto handle_irq; 237 } 238 if (mask & BIT(22)) { 239 mask = BIT(22); 240 irq = 22; 241 goto handle_irq; 242 } 243 } else { 244 if (mask & BIT(23)) { 245 mask = BIT(23); 246 irq = 23; 247 goto handle_irq; 248 } 249 if (mask & BIT(27)) { 250 mask = BIT(27); 251 irq = 27; 252 goto handle_irq; 253 } 254 if (mask & BIT(29)) { 255 mask = BIT(29); 256 irq = 29; 257 goto handle_irq; 258 } 259 } 260 return 0; 261 handle_irq: 262 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 263 return mask; 264 } 265 _xtensa_handle_one_int7(unsigned int mask)266static inline int _xtensa_handle_one_int7(unsigned int mask) 267 { 268 int irq; 269 270 if (mask & BIT(14)) { 271 mask = BIT(14); 272 irq = 14; 273 goto handle_irq; 274 } 275 return 0; 276 handle_irq: 277 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 278 return mask; 279 } 280 _xtensa_handle_one_int5(unsigned int mask)281static inline int _xtensa_handle_one_int5(unsigned int mask) 282 { 283 int irq; 284 285 if (mask & BIT(16)) { 286 mask = BIT(16); 287 irq = 16; 288 goto handle_irq; 289 } 290 if (mask & BIT(26)) { 291 mask = BIT(26); 292 irq = 26; 293 goto handle_irq; 294 } 295 if (mask & BIT(31)) { 296 mask = BIT(31); 297 irq = 31; 298 goto handle_irq; 299 } 300 return 0; 301 handle_irq: 302 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 303 return mask; 304 } 305 _xtensa_handle_one_int2(unsigned int mask)306static inline int _xtensa_handle_one_int2(unsigned int mask) 307 { 308 int irq; 309 310 if (mask & BIT(19)) { 311 mask = BIT(19); 312 irq = 19; 313 goto handle_irq; 314 } 315 if (mask & BIT(20)) { 316 mask = BIT(20); 317 irq = 20; 318 goto handle_irq; 319 } 320 if (mask & BIT(21)) { 321 mask = BIT(21); 322 irq = 21; 323 goto handle_irq; 324 } 325 return 0; 326 handle_irq: 327 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 328 return mask; 329 } 330 _xtensa_handle_one_int4(unsigned int mask)331static inline int _xtensa_handle_one_int4(unsigned int mask) 332 { 333 int irq; 334 335 if (mask & 0x3000000) { 336 if (mask & BIT(24)) { 337 mask = BIT(24); 338 irq = 24; 339 goto handle_irq; 340 } 341 if (mask & BIT(25)) { 342 mask = BIT(25); 343 irq = 25; 344 goto handle_irq; 345 } 346 } else { 347 if (mask & BIT(28)) { 348 mask = BIT(28); 349 irq = 28; 350 goto handle_irq; 351 } 352 if (mask & BIT(30)) { 353 mask = BIT(30); 354 irq = 30; 355 goto handle_irq; 356 } 357 } 358 return 0; 359 handle_irq: 360 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 361 return mask; 362 } 363 _xtensa_handle_one_int0(unsigned int mask)364static inline int _xtensa_handle_one_int0(unsigned int mask) 365 { 366 return 0; 367 } _xtensa_handle_one_int6(unsigned int mask)368static inline int _xtensa_handle_one_int6(unsigned int mask) 369 { 370 return 0; 371 } 372
