1/*
2 * Copyright (c) 2023 Andes Technology Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <mem.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18		cpu0: cpu@0 {
19			compatible = "andestech,andescore-v5", "riscv";
20			device_type = "cpu";
21			reg = <0>;
22			status = "okay";
23			riscv,isa = "rv32gc_xandes";
24			mmu-type = "riscv,sv32";
25			clock-frequency = <60000000>;
26			i-cache-line-size = <32>;
27			d-cache-line-size = <32>;
28			cpu0_intc: interrupt-controller {
29				compatible = "riscv,cpu-intc";
30				#address-cells = <0>;
31				#interrupt-cells = <1>;
32				interrupt-controller;
33			};
34		};
35		cpu1: cpu@1 {
36			compatible = "andestech,andescore-v5", "riscv";
37			device_type = "cpu";
38			reg = <1>;
39			status = "okay";
40			riscv,isa = "rv32gc_xandes";
41			mmu-type = "riscv,sv32";
42			clock-frequency = <60000000>;
43			i-cache-line-size = <32>;
44			d-cache-line-size = <32>;
45			cpu1_intc: interrupt-controller {
46				compatible = "riscv,cpu-intc";
47				#address-cells = <0>;
48				#interrupt-cells = <1>;
49				interrupt-controller;
50			};
51		};
52		cpu2: cpu@2 {
53			compatible = "andestech,andescore-v5", "riscv";
54			device_type = "cpu";
55			reg = <2>;
56			status = "okay";
57			riscv,isa = "rv32gc_xandes";
58			mmu-type = "riscv,sv32";
59			clock-frequency = <60000000>;
60			i-cache-line-size = <32>;
61			d-cache-line-size = <32>;
62			cpu2_intc: interrupt-controller {
63				compatible = "riscv,cpu-intc";
64				#address-cells = <0>;
65				#interrupt-cells = <1>;
66				interrupt-controller;
67			};
68		};
69		cpu3: cpu@3 {
70			compatible = "andestech,andescore-v5", "riscv";
71			device_type = "cpu";
72			reg = <3>;
73			status = "okay";
74			riscv,isa = "rv32gc_xandes";
75			mmu-type = "riscv,sv32";
76			clock-frequency = <60000000>;
77			i-cache-line-size = <32>;
78			d-cache-line-size = <32>;
79			cpu3_intc: interrupt-controller {
80				compatible = "riscv,cpu-intc";
81				#address-cells = <0>;
82				#interrupt-cells = <1>;
83				interrupt-controller;
84			};
85		};
86		cpu4: cpu@4 {
87			compatible = "andestech,andescore-v5", "riscv";
88			device_type = "cpu";
89			reg = <4>;
90			status = "okay";
91			riscv,isa = "rv32gc_xandes";
92			mmu-type = "riscv,sv32";
93			clock-frequency = <60000000>;
94			i-cache-line-size = <32>;
95			d-cache-line-size = <32>;
96			cpu4_intc: interrupt-controller {
97				compatible = "riscv,cpu-intc";
98				#address-cells = <0>;
99				#interrupt-cells = <1>;
100				interrupt-controller;
101			};
102		};
103		cpu5: cpu@5 {
104			compatible = "andestech,andescore-v5", "riscv";
105			device_type = "cpu";
106			reg = <5>;
107			status = "okay";
108			riscv,isa = "rv32gc_xandes";
109			mmu-type = "riscv,sv32";
110			clock-frequency = <60000000>;
111			i-cache-line-size = <32>;
112			d-cache-line-size = <32>;
113			cpu5_intc: interrupt-controller {
114				compatible = "riscv,cpu-intc";
115				#address-cells = <0>;
116				#interrupt-cells = <1>;
117				interrupt-controller;
118			};
119		};
120		cpu6: cpu@6 {
121			compatible = "andestech,andescore-v5", "riscv";
122			device_type = "cpu";
123			reg = <6>;
124			status = "okay";
125			riscv,isa = "rv32gc_xandes";
126			mmu-type = "riscv,sv32";
127			clock-frequency = <60000000>;
128			i-cache-line-size = <32>;
129			d-cache-line-size = <32>;
130			cpu6_intc: interrupt-controller {
131				compatible = "riscv,cpu-intc";
132				#address-cells = <0>;
133				#interrupt-cells = <1>;
134				interrupt-controller;
135			};
136		};
137		cpu7: cpu@7 {
138			compatible = "andestech,andescore-v5", "riscv";
139			device_type = "cpu";
140			reg = <7>;
141			status = "okay";
142			riscv,isa = "rv32gc_xandes";
143			mmu-type = "riscv,sv32";
144			clock-frequency = <60000000>;
145			i-cache-line-size = <32>;
146			d-cache-line-size = <32>;
147			cpu7_intc: interrupt-controller {
148				compatible = "riscv,cpu-intc";
149				#address-cells = <0>;
150				#interrupt-cells = <1>;
151				interrupt-controller;
152			};
153		};
154	};
155
156	dram: memory@0 {
157		device_type = "memory";
158		compatible = "mmio-sram";
159		reg = <0x00000000 0x40000000>;
160	};
161
162	soc {
163		#address-cells = <1>;
164		#size-cells = <1>;
165		compatible = "andestech,ae350";
166		ranges;
167
168		plic0: interrupt-controller@e4000000 {
169			compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
170			#address-cells = <1>;
171			#interrupt-cells = <2>;
172			interrupt-controller;
173			reg = <0xe4000000 0x02000000>;
174			riscv,max-priority = <255>;
175			riscv,ndev = <1023>;
176			interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11
177					       &cpu2_intc 11 &cpu3_intc 11
178					       &cpu4_intc 11 &cpu5_intc 11
179					       &cpu6_intc 11 &cpu7_intc 11>;
180		};
181
182		plic_sw: interrupt-controller@e6400000 {
183			compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
184			#address-cells = <1>;
185			#interrupt-cells = <2>;
186			interrupt-controller;
187			reg = <0xe6400000 0x00400000>;
188			riscv,max-priority = <255>;
189			riscv,ndev = <1023>;
190			interrupts-extended = <&cpu0_intc 3 &cpu1_intc 3
191					       &cpu2_intc 3 &cpu3_intc 3
192					       &cpu4_intc 3 &cpu5_intc 3
193					       &cpu6_intc 3 &cpu7_intc 3>;
194
195			#size-cells = <0>;
196			mbox: mbox-controller@0 {
197				compatible = "andestech,mbox-plic-sw";
198				#mbox-cells = <1>;
199				reg = <0>;
200				interrupts = <9 1>, <10 1>, <11 1>, <12 1>,
201					     <13 1>, <14 1>, <15 1>, <16 1>,
202					     <17 1>, <18 1>, <19 1>, <20 1>,
203					     <21 1>, <22 1>, <23 1>, <24 1>,
204					     <25 1>, <26 1>, <27 1>, <28 1>,
205					     <29 1>, <30 1>, <31 1>;
206				interrupt-names = "mbox_9", "mbox_10", "mbox_11", "mbox_12",
207						  "mbox_13", "mbox_14", "mbox_15", "mbox_16",
208						  "mbox_17", "mbox_18", "mbox_19", "mbox_20",
209						  "mbox_21", "mbox_22", "mbox_23", "mbox_24",
210						  "mbox_25", "mbox_26", "mbox_27", "mbox_28",
211						  "mbox_29", "mbox_30", "mbox_31";
212				interrupt-parent = <&plic_sw>;
213				status = "disabled";
214			};
215		};
216
217		mtimer: timer@e6000000 {
218			compatible = "andestech,machine-timer";
219			reg = <0xe6000000 0x10>;
220			interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7
221					       &cpu2_intc 7 &cpu3_intc 7
222					       &cpu4_intc 7 &cpu5_intc 7
223					       &cpu6_intc 7 &cpu7_intc 7>;
224		};
225
226		syscon: syscon@f0100000 {
227			compatible = "syscon", "andestech,atcsmu100";
228			reg = <0xf0100000 0x1000>;
229			status = "disabled";
230		};
231
232		l2_cache: cache-controller@e0500000 {
233			compatible = "andestech,l2c";
234			reg = <0xe0500000 0x1000>;
235			status = "disabled";
236		};
237
238		uart0: serial@f0200020 {
239			compatible = "ns16550";
240			reg = <0xf0200020 0x1000>;
241			reg-shift = <2>;
242			interrupts = <8 1>;
243			interrupt-parent = <&plic0>;
244			status = "disabled";
245		};
246
247		uart1: serial@f0300020 {
248			compatible = "ns16550";
249			reg = <0xf0300020 0x1000>;
250			reg-shift = <2>;
251			interrupts = <9 1>;
252			interrupt-parent = <&plic0>;
253			status = "disabled";
254		};
255
256		pit0: pit@f0400000 {
257			compatible = "andestech,atcpit100";
258			reg = <0xf0400000 0x1000>;
259			interrupts = <3 1>;
260			interrupt-parent = <&plic0>;
261			clock-frequency = <60000000>;
262			prescaler = <600>;
263			status = "disabled";
264		};
265
266		rtc0: rtc@f0600000 {
267			compatible = "andestech,atcrtc100";
268			reg = <0xf0600000 0x1000>;
269			interrupts = <1 1>, <2 1>;
270			interrupt-parent = <&plic0>;
271			wakeup-source;
272			status = "disabled";
273		};
274
275		gpio0: gpio@f0700000 {
276			compatible = "andestech,atcgpio100";
277			reg = <0xf0700000 0x1000>;
278			interrupts = <7 1>;
279			interrupt-parent = <&plic0>;
280			gpio-controller;
281			ngpios = <32>;
282			#gpio-cells = <2>;
283			status = "disabled";
284		};
285
286		i2c0: i2c@f0a00000 {
287			compatible = "andestech,atciic100";
288			reg = <0xf0a00000 0x1000>;
289			interrupts = <6 1>;
290			interrupt-parent = <&plic0>;
291			#address-cells = <1>;
292			#size-cells = <0>;
293			status = "disabled";
294		};
295
296		spi0: spi@f0b00000 {
297			compatible = "andestech,atcspi200";
298			reg = <0xf0b00000 0x1000
299			       0x80000000 DT_SIZE_K(1024)>;
300			reg-names = "control", "mem";
301			interrupts = <4 1>;
302			interrupt-parent = <&plic0>;
303			dmas = <&dma0 0 0 0x009>,
304			       <&dma0 1 1 0x00A>;
305			dma-names = "tx", "rx";
306			#address-cells = <1>;
307			#size-cells = <0>;
308			clock-frequency = <66000000>;
309			status = "disabled";
310		};
311
312		spi1: spi@f0f00000 {
313			compatible = "andestech,atcspi200";
314			reg = <0xf0f00000 0x1000>;
315			reg-names = "control";
316			interrupts = <5 1>;
317			interrupt-parent = <&plic0>;
318			dmas = <&dma0 2 2 0x009>,
319			       <&dma0 3 3 0x00A>;
320			dma-names = "tx", "rx";
321			#address-cells = <1>;
322			#size-cells = <0>;
323			clock-frequency = <66000000>;
324			status = "disabled";
325		};
326
327		dma0: dma@f0c00000 {
328			compatible = "andestech,atcdmac300";
329			reg = <0xf0c00000 0x1000>;
330			interrupts = <10 1>;
331			interrupt-parent = <&plic0>;
332			dma-channels = <8>;
333			dma-requests = <16>;
334			chain-transfer = <1>;
335			#dma-cells = <3>;
336			status = "disabled";
337		};
338
339		eth0: eth@e0100000 {
340			compatible = "andestech,atfmac100";
341			reg = <0xe0100000 0x1000>;
342			interrupts = <19 2>;
343			interrupt-parent = <&plic0>;
344			local-mac-address = [FC 8C EB 9B A6 51];
345			status = "disabled";
346		};
347
348		lcd0: lcd@e0200000 {
349			compatible = "andestech,atflcdc100";
350			reg = <0xe0200000 0x1000>;
351			interrupts = <20 1>;
352			interrupt-parent = <&plic0>;
353			clock-frequency = <30000000>;
354			status = "disabled";
355		};
356
357		wdt: wdt@f0500000 {
358			compatible = "andestech,atcwdt200";
359			reg = <0xf0500000 0x1000>;
360			interrupts = <20 1>;
361			interrupt-parent = <&plic0>;
362			status = "disabled";
363		};
364
365		smc0: smc@e0400000 {
366			compatible = "andestech,atfsmc020";
367			reg = <0xe0400000 0x1000>;
368			status = "disabled";
369		};
370
371		snd0: snd@f0d00000 {
372			compatible = "andestech,atfac97";
373			reg = <0xf0d00000 0x1000>;
374			interrupts = <17 1>;
375			interrupt-parent = <&plic0>;
376			status = "disabled";
377		};
378
379		mmc0: mmc@f0e00000 {
380			compatible = "andestech,atfsdc010";
381			reg = <0xf0e00000 0x1000>;
382			interrupts = <18 1>;
383			interrupt-parent = <&plic0>;
384			cap-sd-highspeed;
385			max-frequency = <100000000>;
386			clock-freq-min-max = <400000 100000000>;
387			fifo-depth = <0x10>;
388			status = "disabled";
389		};
390	};
391};
392