1 /* 2 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 3 * 4 * Functions here are designed to produce efficient code to 5 * search an Xtensa bitmask of interrupts, inspecting only those bits 6 * declared to be associated with a given interrupt level. Each 7 * dispatcher will handle exactly one flagged interrupt, in numerical 8 * order (low bits first) and will return a mask of that bit that can 9 * then be cleared by the calling code. Unrecognized bits for the 10 * level will invoke an error handler. 11 */ 12 13 #include <xtensa/config/core-isa.h> 14 #include <zephyr/sw_isr_table.h> 15 16 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 17 #error core-isa.h interrupt level does not match dispatcher! 18 #endif 19 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 20 #error core-isa.h interrupt level does not match dispatcher! 21 #endif 22 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 23 #error core-isa.h interrupt level does not match dispatcher! 24 #endif 25 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 26 #error core-isa.h interrupt level does not match dispatcher! 27 #endif 28 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 29 #error core-isa.h interrupt level does not match dispatcher! 30 #endif 31 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 32 #error core-isa.h interrupt level does not match dispatcher! 33 #endif 34 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 35 #error core-isa.h interrupt level does not match dispatcher! 36 #endif 37 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 38 #error core-isa.h interrupt level does not match dispatcher! 39 #endif 40 #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1 41 #error core-isa.h interrupt level does not match dispatcher! 42 #endif 43 #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 1 44 #error core-isa.h interrupt level does not match dispatcher! 45 #endif 46 #if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 47 #error core-isa.h interrupt level does not match dispatcher! 48 #endif 49 #if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 50 #error core-isa.h interrupt level does not match dispatcher! 51 #endif 52 #if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 1 53 #error core-isa.h interrupt level does not match dispatcher! 54 #endif 55 #if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 1 56 #error core-isa.h interrupt level does not match dispatcher! 57 #endif 58 #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 2 59 #error core-isa.h interrupt level does not match dispatcher! 60 #endif 61 #if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3 62 #error core-isa.h interrupt level does not match dispatcher! 63 #endif 64 #if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3 65 #error core-isa.h interrupt level does not match dispatcher! 66 #endif 67 #if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 68 #error core-isa.h interrupt level does not match dispatcher! 69 #endif 70 #if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 3 71 #error core-isa.h interrupt level does not match dispatcher! 72 #endif 73 #if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4 74 #error core-isa.h interrupt level does not match dispatcher! 75 #endif 76 #if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 5 77 #error core-isa.h interrupt level does not match dispatcher! 78 #endif 79 #if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 80 #error core-isa.h interrupt level does not match dispatcher! 81 #endif 82 _xtensa_handle_one_int0(unsigned int mask)83static inline int _xtensa_handle_one_int0(unsigned int mask) 84 { 85 return 0; 86 } 87 _xtensa_handle_one_int1(unsigned int mask)88static inline int _xtensa_handle_one_int1(unsigned int mask) 89 { 90 if (mask & 0x7f) { 91 if (mask & 0x7) { 92 if (mask & (1 << 0)) { 93 struct _isr_table_entry *e = &_sw_isr_table[0]; 94 95 e->isr(e->arg); 96 return 1 << 0; 97 } 98 if (mask & (1 << 1)) { 99 struct _isr_table_entry *e = &_sw_isr_table[1]; 100 101 e->isr(e->arg); 102 return 1 << 1; 103 } 104 if (mask & (1 << 2)) { 105 struct _isr_table_entry *e = &_sw_isr_table[2]; 106 107 e->isr(e->arg); 108 return 1 << 2; 109 } 110 } else { 111 if (mask & 0x18) { 112 if (mask & (1 << 3)) { 113 struct _isr_table_entry *e = &_sw_isr_table[3]; 114 115 e->isr(e->arg); 116 return 1 << 3; 117 } 118 if (mask & (1 << 4)) { 119 struct _isr_table_entry *e = &_sw_isr_table[4]; 120 121 e->isr(e->arg); 122 return 1 << 4; 123 } 124 } else { 125 if (mask & (1 << 5)) { 126 struct _isr_table_entry *e = &_sw_isr_table[5]; 127 128 e->isr(e->arg); 129 return 1 << 5; 130 } 131 if (mask & (1 << 6)) { 132 struct _isr_table_entry *e = &_sw_isr_table[6]; 133 134 e->isr(e->arg); 135 return 1 << 6; 136 } 137 } 138 } 139 } else { 140 if (mask & 0x18080) { 141 if (mask & (1 << 7)) { 142 struct _isr_table_entry *e = &_sw_isr_table[7]; 143 144 e->isr(e->arg); 145 return 1 << 7; 146 } 147 if (mask & (1 << 15)) { 148 struct _isr_table_entry *e = &_sw_isr_table[15]; 149 150 e->isr(e->arg); 151 return 1 << 15; 152 } 153 if (mask & (1 << 16)) { 154 struct _isr_table_entry *e = &_sw_isr_table[16]; 155 156 e->isr(e->arg); 157 return 1 << 16; 158 } 159 } else { 160 if (mask & 0x60000) { 161 if (mask & (1 << 17)) { 162 struct _isr_table_entry *e = &_sw_isr_table[17]; 163 164 e->isr(e->arg); 165 return 1 << 17; 166 } 167 if (mask & (1 << 18)) { 168 struct _isr_table_entry *e = &_sw_isr_table[18]; 169 170 e->isr(e->arg); 171 return 1 << 18; 172 } 173 } else { 174 if (mask & (1 << 19)) { 175 struct _isr_table_entry *e = &_sw_isr_table[19]; 176 177 e->isr(e->arg); 178 return 1 << 19; 179 } 180 if (mask & (1 << 20)) { 181 struct _isr_table_entry *e = &_sw_isr_table[20]; 182 183 e->isr(e->arg); 184 return 1 << 20; 185 } 186 } 187 } 188 } 189 return 0; 190 } 191 _xtensa_handle_one_int2(unsigned int mask)192static inline int _xtensa_handle_one_int2(unsigned int mask) 193 { 194 if (mask & (1 << 8)) { 195 struct _isr_table_entry *e = &_sw_isr_table[8]; 196 197 e->isr(e->arg); 198 return 1 << 8; 199 } 200 return 0; 201 } 202 _xtensa_handle_one_int3(unsigned int mask)203static inline int _xtensa_handle_one_int3(unsigned int mask) 204 { 205 if (mask & 0x600) { 206 if (mask & (1 << 9)) { 207 struct _isr_table_entry *e = &_sw_isr_table[9]; 208 209 e->isr(e->arg); 210 return 1 << 9; 211 } 212 if (mask & (1 << 10)) { 213 struct _isr_table_entry *e = &_sw_isr_table[10]; 214 215 e->isr(e->arg); 216 return 1 << 10; 217 } 218 } else { 219 if (mask & (1 << 11)) { 220 struct _isr_table_entry *e = &_sw_isr_table[11]; 221 222 e->isr(e->arg); 223 return 1 << 11; 224 } 225 if (mask & (1 << 21)) { 226 struct _isr_table_entry *e = &_sw_isr_table[21]; 227 228 e->isr(e->arg); 229 return 1 << 21; 230 } 231 } 232 return 0; 233 } 234 _xtensa_handle_one_int4(unsigned int mask)235static inline int _xtensa_handle_one_int4(unsigned int mask) 236 { 237 if (mask & (1 << 12)) { 238 struct _isr_table_entry *e = &_sw_isr_table[12]; 239 240 e->isr(e->arg); 241 return 1 << 12; 242 } 243 return 0; 244 } 245 _xtensa_handle_one_int5(unsigned int mask)246static inline int _xtensa_handle_one_int5(unsigned int mask) 247 { 248 if (mask & (1 << 13)) { 249 struct _isr_table_entry *e = &_sw_isr_table[13]; 250 251 e->isr(e->arg); 252 return 1 << 13; 253 } 254 return 0; 255 } 256 _xtensa_handle_one_int6(unsigned int mask)257static inline int _xtensa_handle_one_int6(unsigned int mask) 258 { 259 return 0; 260 } 261 _xtensa_handle_one_int7(unsigned int mask)262static inline int _xtensa_handle_one_int7(unsigned int mask) 263 { 264 if (mask & (1 << 14)) { 265 struct _isr_table_entry *e = &_sw_isr_table[14]; 266 267 e->isr(e->arg); 268 return 1 << 14; 269 } 270 return 0; 271 } 272
