1 /* Copyright (c) 2022 Intel Corporation 2 * SPDX-License-Identifier: Apache-2.0 3 */ 4 /* 5 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 6 * 7 * Functions here are designed to produce efficient code to 8 * search an Xtensa bitmask of interrupts, inspecting only those bits 9 * declared to be associated with a given interrupt level. Each 10 * dispatcher will handle exactly one flagged interrupt, in numerical 11 * order (low bits first) and will return a mask of that bit that can 12 * then be cleared by the calling code. Unrecognized bits for the 13 * level will invoke an error handler. 14 */ 15 16 #include <xtensa/config/core-isa.h> 17 #include <zephyr/sys/util.h> 18 #include <zephyr/sw_isr_table.h> 19 20 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 21 #error core-isa.h interrupt level does not match dispatcher! 22 #endif 23 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 24 #error core-isa.h interrupt level does not match dispatcher! 25 #endif 26 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2 27 #error core-isa.h interrupt level does not match dispatcher! 28 #endif 29 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 2 30 #error core-isa.h interrupt level does not match dispatcher! 31 #endif 32 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2 33 #error core-isa.h interrupt level does not match dispatcher! 34 #endif 35 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 3 36 #error core-isa.h interrupt level does not match dispatcher! 37 #endif 38 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 3 39 #error core-isa.h interrupt level does not match dispatcher! 40 #endif 41 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 3 42 #error core-isa.h interrupt level does not match dispatcher! 43 #endif 44 #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 5 45 #error core-isa.h interrupt level does not match dispatcher! 46 #endif 47 _xtensa_handle_one_int1(unsigned int mask)48static inline int _xtensa_handle_one_int1(unsigned int mask) 49 { 50 int irq; 51 52 if (mask & BIT(0)) { 53 mask = BIT(0); 54 irq = 0; 55 goto handle_irq; 56 } 57 if (mask & BIT(1)) { 58 mask = BIT(1); 59 irq = 1; 60 goto handle_irq; 61 } 62 return 0; 63 handle_irq: 64 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 65 return mask; 66 } 67 _xtensa_handle_one_int2(unsigned int mask)68static inline int _xtensa_handle_one_int2(unsigned int mask) 69 { 70 int irq; 71 72 if (mask & BIT(2)) { 73 mask = BIT(2); 74 irq = 2; 75 goto handle_irq; 76 } 77 if (mask & BIT(3)) { 78 mask = BIT(3); 79 irq = 3; 80 goto handle_irq; 81 } 82 if (mask & BIT(4)) { 83 mask = BIT(4); 84 irq = 4; 85 goto handle_irq; 86 } 87 return 0; 88 handle_irq: 89 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 90 return mask; 91 } 92 _xtensa_handle_one_int3(unsigned int mask)93static inline int _xtensa_handle_one_int3(unsigned int mask) 94 { 95 int irq; 96 97 if (mask & BIT(5)) { 98 mask = BIT(5); 99 irq = 5; 100 goto handle_irq; 101 } 102 if (mask & BIT(6)) { 103 mask = BIT(6); 104 irq = 6; 105 goto handle_irq; 106 } 107 if (mask & BIT(7)) { 108 mask = BIT(7); 109 irq = 7; 110 goto handle_irq; 111 } 112 return 0; 113 handle_irq: 114 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 115 return mask; 116 } 117 _xtensa_handle_one_int5(unsigned int mask)118static inline int _xtensa_handle_one_int5(unsigned int mask) 119 { 120 /* It is a Non-maskable interrupt handler. 121 * The non-maskable interrupt have no corresponding bit in INTERRUPT and INTENABLE registers 122 * so mask parameter is always 0. 123 */ 124 _sw_isr_table[8].isr(_sw_isr_table[8].arg); 125 return 0; 126 } 127 _xtensa_handle_one_int0(unsigned int mask)128static inline int _xtensa_handle_one_int0(unsigned int mask) 129 { 130 return 0; 131 } _xtensa_handle_one_int4(unsigned int mask)132static inline int _xtensa_handle_one_int4(unsigned int mask) 133 { 134 return 0; 135 } 136
