1# Copyright (c) 2021 Andes Technology Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_SERIES_ANDES_AE350
5	select RISCV
6	select RISCV_PRIVILEGED
7	select RISCV_HAS_PLIC
8	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
9	imply XIP
10
11config SOC_ANDES_AE350
12	select ATOMIC_OPERATIONS_BUILTIN
13	select INCLUDE_RESET_VECTOR
14	select RISCV_ISA_EXT_M
15	select RISCV_ISA_EXT_A
16	select RISCV_ISA_EXT_C
17	select CPU_HAS_DCACHE
18	select CPU_HAS_ICACHE
19	select CACHE_MANAGEMENT if DCACHE
20	select RISCV_PMP
21
22if SOC_SERIES_ANDES_AE350
23
24choice
25prompt "Base CPU ISA options"
26default RV32I_CPU
27
28config RV32I_CPU
29	bool "RISCV32 CPU ISA"
30	select RISCV_ISA_RV32I
31	select RISCV_ISA_EXT_ZICSR
32	select RISCV_ISA_EXT_ZIFENCEI
33
34config RV32E_CPU
35	bool "RISCV32E CPU ISA"
36	select RISCV_ISA_RV32E
37	select RISCV_ISA_EXT_ZICSR
38	select RISCV_ISA_EXT_ZIFENCEI
39
40config RV64I_CPU
41	bool "RISCV64 CPU ISA"
42	select RISCV_ISA_RV64I
43	select RISCV_ISA_EXT_ZICSR
44	select RISCV_ISA_EXT_ZIFENCEI
45	select 64BIT
46
47endchoice
48
49choice
50prompt "FPU options"
51default NO_FPU
52
53config NO_FPU
54	bool "No FPU"
55
56config SINGLE_PRECISION_FPU
57	bool "Single precision FPU"
58	select CPU_HAS_FPU
59
60config DOUBLE_PRECISION_FPU
61	bool "Double precision FPU"
62	select CPU_HAS_FPU_DOUBLE_PRECISION
63
64endchoice
65
66config SOC_ANDES_V5_HWDSP
67	bool "AndeStar V5 DSP ISA"
68	select RISCV_SOC_CONTEXT_SAVE
69	depends on !RISCV_GENERIC_TOOLCHAIN
70	help
71		This option enables the AndeStar v5 hardware DSP, in order to
72		support using the DSP instructions.
73
74config SOC_ANDES_V5_PFT
75	bool "Andes V5 PowerBrake extension"
76	default y
77	select RISCV_SOC_CONTEXT_SAVE
78	help
79		The PowerBrake extension throttles performance by reducing instruction
80		executing rate.
81
82config SOC_ANDES_V5_EXECIT
83	bool "Andes V5 EXEC.IT extension"
84	depends on RISCV_ISA_EXT_C
85	depends on !RISCV_GENERIC_TOOLCHAIN
86	depends on !LINKER_USE_NO_RELAX
87	help
88		The EXEC.IT extension (Execution on Instruction Table) generate
89		a look-up table and replaces suitable 32-bit instructions with
90		the 16-bit "exec.it <INDEX>".
91
92config SOC_ANDES_V5_PMA
93	bool "Andes V5 Physical Memory Attribute (PMA)"
94	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
95	select SOC_EARLY_INIT_HOOK
96	select SOC_PER_CORE_INIT_HOOK
97	help
98		This option enables the Andes V5 PMA, in order to support SW to
99		configure physical memory attribute by PMA CSRs. The address
100		matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
101		(power-of-two alignment).
102
103config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE
104	int
105	depends on SOC_ANDES_V5_PMA
106	default 4096
107	help
108		Minimum size (and alignment) of an PMA region. Use this symbol
109		to guarantee minimum size and alignment of PMA regions.
110
111config SOC_ANDES_V5_L2C
112	bool
113	select DEPRECATED
114
115config SOC_ANDES_V5_IOCP
116	bool "Andes V5 I/O Coherence Port (IOCP)"
117	depends on DCACHE
118	help
119		Support Andes V5 I/O Coherence Port to handle cache coherency
120		between cache and external non-caching master, such as DMA
121		controller.
122
123endif # SOC_SERIES_ANDES_AE350
124