1# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_NEORV32
5	select RISCV
6	select RISCV_ISA_RV32I
7	select RISCV_ISA_EXT_M
8	select RISCV_ISA_EXT_A
9	select RISCV_ISA_EXT_ZICSR
10	select RISCV_ISA_EXT_ZIFENCEI
11	select RISCV_PRIVILEGED
12	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
13	imply XIP
14
15if SOC_NEORV32
16
17config SOC_NEORV32_V1_8_6
18	bool "v1.8.6"
19	# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
20	select ATOMIC_OPERATIONS_C
21
22config SOC_NEORV32_VERSION
23	hex
24	default 0x01080600 if SOC_NEORV32_V1_8_6
25	help
26	  The targeted NEORV32 version as BCD-coded number. The format is
27	  identical to that of the NEORV32 Machine implementation ID (mimpid)
28	  register.
29
30config SOC_NEORV32_ISA_C
31	bool "RISC-V ISA Extension \"C\""
32	select RISCV_ISA_EXT_C
33	help
34	  Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
35	  "C" extension (Compressed Instructions).
36
37endif # SOC_NEORV32
38