1# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_NEORV32
5	bool
6	help
7	  NEORV32 Processor (SoC).
8
9	  The NEORV32 CPU implementation must have the following RISC-V ISA
10	  extensions enabled in order to support Zephyr:
11	  - M (Integer Multiplication and Division)
12	  - Zicsr (Control and Status Register (CSR) Instructions)
13
14	  The following NEORV32 CPU ISA extensions are not currently supported
15	  by Zephyr and can safely be disabled:
16	  - A (Atomic Instructions)
17	  - E (Embedded, only 16 integer registers)
18	  - Zbb (Basic Bit Manipulation)
19	  - Zfinx (Floating Point in Integer Registers)
20
21config SOC
22	default "neorv32" if SOC_NEORV32
23