1#include <xtensa/config/core-isa.h> 2 3/* 4 * Not a C source code file. 5 * 6 * Intended to be preprocessed only, to produce output for 7 * interpretation by the xtensa-int-handlers.py script. Literally all 8 * this does is emit records for which interrupts are at which level, 9 * available per-hardware by an SDK-provided core-isa.h file. 10 */ 11 12__xtensa_int_level_magic__ 0 XCHAL_INT0_LEVEL 13__xtensa_int_level_magic__ 1 XCHAL_INT1_LEVEL 14__xtensa_int_level_magic__ 2 XCHAL_INT2_LEVEL 15__xtensa_int_level_magic__ 3 XCHAL_INT3_LEVEL 16__xtensa_int_level_magic__ 4 XCHAL_INT4_LEVEL 17__xtensa_int_level_magic__ 5 XCHAL_INT5_LEVEL 18__xtensa_int_level_magic__ 6 XCHAL_INT6_LEVEL 19__xtensa_int_level_magic__ 7 XCHAL_INT7_LEVEL 20__xtensa_int_level_magic__ 8 XCHAL_INT8_LEVEL 21__xtensa_int_level_magic__ 9 XCHAL_INT9_LEVEL 22__xtensa_int_level_magic__ 10 XCHAL_INT10_LEVEL 23__xtensa_int_level_magic__ 11 XCHAL_INT11_LEVEL 24__xtensa_int_level_magic__ 12 XCHAL_INT12_LEVEL 25__xtensa_int_level_magic__ 13 XCHAL_INT13_LEVEL 26__xtensa_int_level_magic__ 14 XCHAL_INT14_LEVEL 27__xtensa_int_level_magic__ 15 XCHAL_INT15_LEVEL 28__xtensa_int_level_magic__ 16 XCHAL_INT16_LEVEL 29__xtensa_int_level_magic__ 17 XCHAL_INT17_LEVEL 30__xtensa_int_level_magic__ 18 XCHAL_INT18_LEVEL 31__xtensa_int_level_magic__ 19 XCHAL_INT19_LEVEL 32__xtensa_int_level_magic__ 20 XCHAL_INT20_LEVEL 33__xtensa_int_level_magic__ 21 XCHAL_INT21_LEVEL 34__xtensa_int_level_magic__ 22 XCHAL_INT22_LEVEL 35__xtensa_int_level_magic__ 23 XCHAL_INT23_LEVEL 36__xtensa_int_level_magic__ 24 XCHAL_INT24_LEVEL 37__xtensa_int_level_magic__ 25 XCHAL_INT25_LEVEL 38__xtensa_int_level_magic__ 26 XCHAL_INT26_LEVEL 39__xtensa_int_level_magic__ 27 XCHAL_INT27_LEVEL 40__xtensa_int_level_magic__ 28 XCHAL_INT28_LEVEL 41__xtensa_int_level_magic__ 29 XCHAL_INT29_LEVEL 42__xtensa_int_level_magic__ 30 XCHAL_INT30_LEVEL 43__xtensa_int_level_magic__ 31 XCHAL_INT31_LEVEL 44
