| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | cc13xx_cc26xx-pinctrl.h | 2 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated
4 * SPDX-License-Identifier: Apache-2.0
14 #define IOC_PORT_AON_CLK32K 0x00000007 /* AON External 32kHz clock */
19 #define IOC_PORT_MCU_SSI0_CLK 0x0000000C /* MCU SSI0 Clock Pin */
21 #define IOC_PORT_MCU_I2C_MSSCL 0x0000000E /* MCU I2C Clock Pin */
42 #define IOC_PORT_MCU_SSI1_CLK 0x00000024 /* MCU SSI1 Clock Pin */
45 #define IOC_PORT_MCU_I2S_WCLK 0x00000027 /* MCU I2S Frame/Word Clock */
46 #define IOC_PORT_MCU_I2S_BCLK 0x00000028 /* MCU I2S Bit Clock */
47 #define IOC_PORT_MCU_I2S_MCLK 0x00000029 /* MCU I2S Master clock 2 */
48 #define IOC_PORT_RFC_TRC 0x0000002E /* RF Core Tracer */
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| /Zephyr-latest/soc/nxp/imx/imx6sx/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
18 /* Move M4 core to the configured RDC domain */ in SOC_RdcInit()
21 /* Set access to WDOG3 for M4 core */ in SOC_RdcInit()
27 /* Set access to UART_1 for M4 core */ in SOC_RdcInit()
31 /* Set access to UART_2 for M4 core */ in SOC_RdcInit()
35 /* Set access to UART_3 for M4 core */ in SOC_RdcInit()
39 /* Set access to UART_4 for M4 core */ in SOC_RdcInit()
43 /* Set access to UART_5 for M4 core */ in SOC_RdcInit()
47 /* Set access to UART_6 for M4 core */ in SOC_RdcInit()
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| /Zephyr-latest/soc/nxp/lpc/lpc54xxx/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
32 /* Memcpy macro to copy segments from secondary core image stored in flash
33 * to RAM section that secondary core boots from.
37 memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \
44 * @brief Initialize the system clock
53 /* Set up the clock sources */ in clock_init()
64 /* Set FLASH wait states for core */ in clock_init()
74 /* Set up clock selectors - Attach clocks to the peripheries */ in clock_init()
78 /* Attach 12 MHz clock to FLEXCOMM0 */ in clock_init()
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| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
35 bool "LPC54114 Cortex-M0 second core"
37 Driver for second core startup
41 hex "Address the second core will boot at"
44 This is the address the second core will boot from. Additionally this
49 DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
51 # Move the LMA address of second core into flash
54 default "-0x20010000+\
62 bool "Clock LPC54XXX SRAM2"
66 will enable the clock to this RAM bank. Disable this Kconfig to leave
|
| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32wba-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
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| D | nuvoton,npcm-pcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton, NPCM PCC (Power and Clock Controller) node.
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
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| D | st,stm32-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-prescaler = <1>;
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| D | nuvoton,numaker-scc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton NuMaker System Clock Controller (SCC)
6 compatible: "nuvoton,numaker-scc"
8 include: [clock-controller.yaml, base.yaml]
19 - "untouched"
20 - "enable"
21 - "disable"
26 Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT)
28 - "untouched"
29 - "enable"
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| D | microchip,xec-pcr.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
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| D | nuvoton,npcx-pcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton, NPCX PCC (Power and Clock Controller) node.
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
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| D | st,stm32h7-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7 devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
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| /Zephyr-latest/soc/nxp/kinetis/k8x/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
35 int "Freescale K8x core clock divider"
38 This option specifies the divide value for the K8x processor core clock
39 from the system clock.
42 int "Freescale K8x bus clock divider"
45 This option specifies the divide value for the K8x bus clock from the
46 system clock.
49 int "Freescale K8x FlexBus clock divider"
52 This option specifies the divide value for the K8x FlexBus clock from the
53 system clock.
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| /Zephyr-latest/soc/nxp/lpc/lpc55xxx/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
97 core clock value at it's highest frequency which clocks at 150MHz.
99 this PLL should not be used as the core clock in those cases.
102 bool "LPC55xxx's second core"
106 hex "Address the second core will boot at"
109 This is the address the second core will boot from.
112 bool "CLock LPC SRAM banks"
|
| D | soc.c | 1 /* Copyright 2017, 2019-2023 NXP
3 * SPDX-License-Identifier: Apache-2.0
10 * This module provides routines to initialize and support board-level
38 /* System clock frequency */
77 * @brief Initialize the system clock
93 /* Set up the clock sources */ in clock_init()
97 /* Set up FRO to the 12 MHz, to ensure we can change the clock freq */ in clock_init()
99 /* Switch to FRO 12MHz first to ensure we can change the clock */ in clock_init()
103 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; in clock_init()
104 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; in clock_init()
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| /Zephyr-latest/soc/nuvoton/npcx/ |
| D | Kconfig | 1 # Nuvoton Cortex-M4 Embedded Controller
4 # SPDX-License-Identifier: Apache-2.0
44 prompt "Clock rate to use for SPI flash"
47 This selects the max clock rate that will be used for loading firmware
51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
103 prompt "Core clock to SPI flash clock ratio"
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| /Zephyr-latest/boards/infineon/cy8cproto_063_ble/ |
| D | cy8cproto_063_ble.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "cy8cproto_063_ble-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "CY8CPROTO-063-BLE PSOC™ 6 BLE Prototyping Kit";
19 uart-5 = &uart5;
29 zephyr,shell-uart = &uart5;
30 zephyr,bt-hci = &bluetooth;
33 /delete-node/ cpu@0;
36 compatible = "gpio-leds";
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| /Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/ |
| D | soc.c | 2 * Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
20 /* Move M4 core to specific RDC domain 1 */ in SOC_RdcInit()
27 * The M4 core is running at domain 1, enable clock gate for in SOC_RdcInit()
37 * The M4 core is running at domain 1, enable the PLL clock sources in SOC_RdcInit()
66 /* Switch cortex-m4 to SYSTEM PLL1 DIV3 */ in SOC_ClockInit()
73 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
79 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
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| /Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/ |
| D | cy8ckit_062s2_ai.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "CY8CKIT-062S2-AI PSOC 6 AI Evaluation Kit";
18 zephyr,shell-uart = &uart5;
30 compatible = "gpio-leds";
42 compatible = "gpio-keys";
53 clock-frequency = <100000000>;
57 clock-div = <1>;
61 /* CM4 core clock = 100MHz
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
20 /* Move M7 core to specific RDC domain 1 */ in SOC_RdcInit()
32 * The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in SOC_RdcInit()
33 * in domain 1 in the CCM. In this way, to ensure the clock of the peripherals used by M in SOC_RdcInit()
34 * core not be affected by A core which is running at domain 0. in SOC_RdcInit()
86 * The following steps just show how to configure the PLL clock sources using the clock in SOC_ClockInit()
87 * driver on M7 core side . Please note that the ROM has already configured the SYSTEM PLL1 in SOC_ClockInit()
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | microchip,xec-pwmbbled.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwmbbled"
27 clock-select:
31 Clock source selection: 32 KHz is available in deep sleep.
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
35 - "PWM_BBLED_CLK_32K"
36 - "PWM_BBLED_CLK_48M"
38 pinctrl-0:
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| /Zephyr-latest/soc/intel/intel_adsp/common/include/ |
| D | cavs-idc.h | 4 * SPDX-License-Identifier: Apache-2.0
16 * Each core has a set of registers its is supposed to use, but all
20 * Each core has a "ITC" register associated with each other core in
22 * ITC register, an IDC interrupt is latched for the target core.
26 * On the target core, there is a "TFC" register for each core that
40 * So you can send a synchronous message from core "src" (where src is
41 * the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to
42 * core "dst" with:
44 * IDC[src].core[dst].itc = BIT(31) | message;
45 * while (IDC[src].core[dst].itc & BIT(31)) {}
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| D | adsp_clk.h | 4 * SPDX-License-Identifier: Apache-2.0
20 /** @brief Set cAVS clock frequency
22 * Set xtensa core clock speed.
24 * @param freq Clock frequency index to be set
26 * @return 0 on success, -EINVAL if freq_idx is not valid
30 /** @brief Get list of cAVS clock information
32 * Returns an array of clock information, one for each core.
34 * @return array with clock information
65 /* Clock sources used by dai */
84 /** @brief Check if clock source is supported
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| /Zephyr-latest/boards/infineon/cy8cproto_062_4343w/ |
| D | cy8cproto_062_4343w.dts | 3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "cy8cproto_062_4343w-common.dtsi"
10 #include "cy8cproto_062_4343w-pinctrl.dtsi"
17 uart-5 = &uart5;
18 i2c-0 = &i2c3;
27 zephyr,shell-uart = &uart5;
28 zephyr,bt-hci = &bt_hci_uart;
37 compatible = "infineon,cat1-uart";
39 current-speed = <115200>;
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
20 /* Move M4 core to specific RDC domain 1 */ in SOC_RdcInit()
27 * The M4 core is running at domain 1, enable clock gate for in SOC_RdcInit()
39 * The M4 core is running at domain 1, enable the PLL clock sources in SOC_RdcInit()
94 /* Switch cortex-m4 to SYSTEM PLL1 */ in SOC_ClockInit()
101 /* Set root clock to 800MHZ/ 2= 400MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
116 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | soc.c | 2 * Copyright 2021-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
25 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
28 /* Memcpy macro to copy segments from secondary core image stored in flash
29 * to RAM section that secondary core boots from.
33 memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_##n) - ADJUSTED_LMA), \
47 /* Dual core mode is enabled, and messaging unit is present */
72 "ARM PLL must have clock-mult property");
74 "ARM PLL must have clock-div property");
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