1 /* Copyright 2017, 2019-2023 NXP
2 *
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 /**
7 * @file
8 * @brief System/hardware module for nxp_lpc55s69 platform
9 *
10 * This module provides routines to initialize and support board-level
11 * hardware for the nxp_lpc55s69 platform.
12 */
13
14 #include <zephyr/kernel.h>
15 #include <zephyr/device.h>
16 #include <zephyr/init.h>
17 #include <soc.h>
18 #include <zephyr/drivers/uart.h>
19 #include <zephyr/linker/sections.h>
20 #include <zephyr/arch/cpu.h>
21 #include <cortex_m/exception.h>
22 #include <fsl_power.h>
23 #include <fsl_clock.h>
24 #include <fsl_common.h>
25 #include <fsl_device_registers.h>
26 #ifdef CONFIG_GPIO_MCUX_LPC
27 #include <fsl_pint.h>
28 #endif
29 #if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
30 #include "usb_phy.h"
31 #include "usb.h"
32 #endif
33 #if defined(CONFIG_SOC_LPC55S36) && (defined(CONFIG_ADC_MCUX_LPADC) \
34 || defined(CONFIG_DAC_MCUX_LPDAC))
35 #include <fsl_vref.h>
36 #endif
37
38 /* System clock frequency */
39 extern uint32_t SystemCoreClock;
40
41 /*Should be in the range of 12MHz to 32MHz */
42 static uint32_t ExternalClockFrequency;
43
44
45 #define CTIMER_CLOCK_SOURCE(node_id) \
46 TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source))
47 #define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val)
48 #define TO_CLOCK_ATTACH_ID(inst, val) MUX_A(CM_CTIMERCLKSEL##inst, val)
49 #define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id));
50
51 #ifdef CONFIG_INIT_PLL0
52 const pll_setup_t pll0Setup = {
53 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(2U) |
54 SYSCON_PLL0CTRL_SELP(31U),
55 .pllndec = SYSCON_PLL0NDEC_NDIV(125U),
56 .pllpdec = SYSCON_PLL0PDEC_PDIV(8U),
57 .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(3072U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
58 .pllRate = 24576000U,
59 .flags = PLL_SETUPFLAG_WAITLOCK
60 };
61 #endif
62
63 #ifdef CONFIG_INIT_PLL1
64 const pll_setup_t pll1Setup = {
65 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) |
66 SYSCON_PLL1CTRL_SELP(31U),
67 .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
68 .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
69 .pllmdec = SYSCON_PLL1MDEC_MDIV(144U),
70 .pllRate = 144000000U,
71 .flags = PLL_SETUPFLAG_WAITLOCK
72 };
73 #endif
74
75 /**
76 *
77 * @brief Initialize the system clock
78 *
79 */
80
clock_init(void)81 static ALWAYS_INLINE void clock_init(void)
82 {
83 ExternalClockFrequency = 0;
84
85 #if defined(CONFIG_SOC_LPC55S36)
86 /* Power Management Controller initialization */
87 POWER_PowerInit();
88 #endif
89
90 #if defined(CONFIG_SOC_LPC55S06) || defined(CONFIG_SOC_LPC55S16) || \
91 defined(CONFIG_SOC_LPC55S26) || defined(CONFIG_SOC_LPC55S28) || \
92 defined(CONFIG_SOC_LPC55S36) || defined(CONFIG_SOC_LPC55S69_CPU0)
93 /* Set up the clock sources */
94 /* Configure FRO192M */
95 /* Ensure FRO is on */
96 POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
97 /* Set up FRO to the 12 MHz, to ensure we can change the clock freq */
98 CLOCK_SetupFROClocking(12000000U);
99 /* Switch to FRO 12MHz first to ensure we can change the clock */
100 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
101
102 /* Ensure CLK_IN is on */
103 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;
104 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
105
106 /* Setting the Core Clock to either 96MHz or in the case of using PLL, 144MHz */
107 #if defined(CONFIG_SOC_LPC55S06) || !defined(CONFIG_INIT_PLL1)
108 SystemCoreClock = 96000000U;
109 #else
110 SystemCoreClock = 144000000U;
111 #endif
112
113
114 /* These functions must be called before increasing to a higher frequency
115 * Additionally, CONFIG_TRUSTED_EXECUTION_NONSECURE is being used
116 * since the non-secure SOCs should not have access to the flash
117 * as this will cause a secure fault to occur
118 */
119 #if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
120 /* Set Voltage for one of the fastest clock outputs: System clock output */
121 POWER_SetVoltageForFreq(SystemCoreClock);
122 /*!< Set FLASH wait states for core */
123 CLOCK_SetFLASHAccessCyclesForFreq(SystemCoreClock);
124 #endif /* !CONFIG_TRUSTED_EXECUTION_NONSECURE */
125
126
127 #if defined(CONFIG_INIT_PLL0) || defined(CONFIG_INIT_PLL1)
128 /* Configure XTAL32M */
129 ExternalClockFrequency = 16000000U;
130 CLOCK_SetupExtClocking(ExternalClockFrequency);
131 #endif
132
133 #if defined(CONFIG_SOC_LPC55S06) || !defined(CONFIG_INIT_PLL1)
134 /* Enable FRO HF(SystemCoreClock) output (Default expected value 96MHz) */
135 CLOCK_SetupFROClocking(SystemCoreClock);
136
137 /* Switch MAIN_CLK to FRO_HF */
138 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
139
140 #else
141 /* Switch PLL1 clock source selector to XTAL32M */
142 CLOCK_AttachClk(kEXT_CLK_to_PLL1);
143
144 /* Ensure PLL1 is on */
145 POWER_DisablePD(kPDRUNCFG_PD_PLL1);
146
147 /* Configure PLL to the desired values */
148 CLOCK_SetPLL1Freq(&pll1Setup);
149
150 /* Switch MAIN_CLK to FRO_HF */
151 CLOCK_AttachClk(kPLL1_to_MAIN_CLK);
152
153 #endif /* CONFIG_SOC_LPC55S06 || !CONFIG_INIT_PLL1 */
154
155
156 #ifdef CONFIG_INIT_PLL0
157 /* Switch PLL0 clock source selector to XTAL32M */
158 CLOCK_AttachClk(kEXT_CLK_to_PLL0);
159
160 /* Configure PLL to the desired values */
161 CLOCK_SetPLL0Freq(&pll0Setup);
162
163 #if defined(CONFIG_SOC_LPC55S36)
164 CLOCK_SetClkDiv(kCLOCK_DivPllClk, 0U, true);
165 CLOCK_SetClkDiv(kCLOCK_DivPllClk, 1U, false);
166 #else
167 CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);
168 CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 1U, false);
169 #endif /* CONFIG_SOC_LPC55S36 */
170 #endif /* CONFIG_INIT_PLL0 */
171
172
173 /* Set up dividers */
174 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
175
176 /* Enables the clock for the I/O controller.: Enable Clock. */
177 CLOCK_EnableClock(kCLOCK_Iocon);
178
179 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_usart, okay)
180 #if defined(CONFIG_SOC_LPC55S36)
181 CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 0U, true);
182 CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1U, false);
183 #endif
184 CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
185 #endif
186
187 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_usart, okay)
188 CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3);
189 #endif
190
191 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay)
192 #if defined(CONFIG_SOC_LPC55S36)
193 CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 0U, true);
194 CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1U, false);
195 #endif
196 /* attach 12 MHz clock to FLEXCOMM4 */
197 CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
198 #endif
199
200 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_usart, okay)
201 CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM4);
202 #endif
203
204 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_usart, okay)
205 CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM5);
206 #endif
207
208 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_usart, okay)
209 CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM6);
210 #endif
211
212 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_usart, okay)
213 CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM7);
214 #endif
215
216 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(hs_lspi))
217 /* Attach 12 MHz clock to HSLSPI */
218 CLOCK_AttachClk(kFRO_HF_DIV_to_HSLSPI);
219 #endif
220
221 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay)
222 /* Enable 1 MHz FRO clock for WWDT */
223 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;
224 #endif
225
226 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(mailbox0), nxp_lpc_mailbox, okay)
227 CLOCK_EnableClock(kCLOCK_Mailbox);
228 #endif
229
230 #if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
231
232 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(usbfs), nxp_lpcip3511, okay)
233 /*< Turn on USB Phy */
234 #if defined(CONFIG_SOC_LPC55S36)
235 POWER_DisablePD(kPDRUNCFG_PD_USBFSPHY);
236 #else
237 POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
238 #endif
239 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
240 #if defined(CONFIG_SOC_LPC55S36)
241 CLOCK_AttachClk(kFRO_HF_to_USB0);
242 #else
243 CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
244 #endif
245 /* enable usb0 host clock */
246 CLOCK_EnableClock(kCLOCK_Usbhsl0);
247 /*
248 * According to reference mannual, device mode setting has to be set by access
249 * usb host register
250 */
251 USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
252 /* disable usb0 host clock */
253 CLOCK_DisableClock(kCLOCK_Usbhsl0);
254
255 /* enable USB IP clock */
256 CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFroHfFreq());
257 #if defined(FSL_FEATURE_USB_USB_RAM) && (FSL_FEATURE_USB_USB_RAM)
258 memset((uint8_t *)FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USB_USB_RAM);
259 #endif
260
261 #endif /* USB_DEVICE_TYPE_FS */
262
263 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(usbhs), nxp_lpcip3511, okay)
264 /* enable usb1 host clock */
265 CLOCK_EnableClock(kCLOCK_Usbh1);
266 /* Put PHY powerdown under software control */
267 USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK;
268 /*
269 * According to reference manual, device mode setting has to be set by
270 * access usb host register
271 */
272 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
273 /* disable usb1 host clock */
274 CLOCK_DisableClock(kCLOCK_Usbh1);
275
276 /* enable USB IP clock */
277 CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, CLK_CLK_IN);
278 CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
279 #if CONFIG_USB_DC_NXP_LPCIP3511
280 USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_CLK_IN, NULL);
281 #endif
282 #if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
283 memset((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM);
284 #endif
285
286 #endif /* USB_DEVICE_TYPE_HS */
287
288 #endif /* CONFIG_USB_DC_NXP_LPCIP3511 */
289
290 DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
291
292 DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)
293
294 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay))
295 #if defined(CONFIG_SOC_LPC55S36)
296 CLOCK_SetClkDiv(kCLOCK_DivFlexcom6Clk, 0U, true);
297 CLOCK_SetClkDiv(kCLOCK_DivFlexcom6Clk, 1U, false);
298 #endif
299 /* attach PLL0 clock to FLEXCOMM6 */
300 CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM6);
301 #endif
302
303 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_i2s, okay))
304 #if defined(CONFIG_SOC_LPC55S36)
305 CLOCK_SetClkDiv(kCLOCK_DivFlexcom7Clk, 0U, true);
306 CLOCK_SetClkDiv(kCLOCK_DivFlexcom7Clk, 1U, false);
307 #endif
308 /* attach PLL0 clock to FLEXCOMM7 */
309 CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM7);
310 #endif
311
312 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(can0), nxp_lpc_mcan, okay)
313 CLOCK_SetClkDiv(kCLOCK_DivCanClk, 1U, false);
314 CLOCK_AttachClk(kMCAN_DIV_to_MCAN);
315 #endif
316
317 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(sdif), nxp_lpc_sdif, okay) && \
318 CONFIG_MCUX_SDIF
319 /* attach main clock to SDIF */
320 CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK);
321 CLOCK_SetClkDiv(kCLOCK_DivSdioClk, 3, true);
322 #endif
323
324 #endif /* CONFIG_SOC_LPC55S69_CPU0 */
325
326 #if defined(CONFIG_SOC_LPC55S36) && defined(CONFIG_PWM)
327 /* Set the Submodule Clocks for FlexPWM */
328 SYSCON->PWM0SUBCTL |=
329 (SYSCON_PWM0SUBCTL_CLK0_EN_MASK | SYSCON_PWM0SUBCTL_CLK1_EN_MASK |
330 SYSCON_PWM0SUBCTL_CLK2_EN_MASK);
331 SYSCON->PWM1SUBCTL |=
332 (SYSCON_PWM1SUBCTL_CLK0_EN_MASK | SYSCON_PWM1SUBCTL_CLK1_EN_MASK |
333 SYSCON_PWM1SUBCTL_CLK2_EN_MASK);
334 #endif
335
336 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(adc0), nxp_lpc_lpadc, okay)
337 #if defined(CONFIG_SOC_LPC55S36)
338 CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 2U, true);
339 CLOCK_AttachClk(kFRO_HF_to_ADC0);
340 #else /* not LPC55s36 */
341 CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk,
342 DT_PROP(DT_NODELABEL(adc0), clk_divider), true);
343 CLOCK_AttachClk(MUX_A(CM_ADCASYNCCLKSEL, DT_PROP(DT_NODELABEL(adc0), clk_source)));
344
345 /* Power up the ADC */
346 POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
347 #endif /* SOC platform */
348 #endif /* ADC */
349
350 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(vref0), nxp_vref, okay))
351 CLOCK_EnableClock(kCLOCK_Vref);
352 POWER_DisablePD(kPDRUNCFG_PD_VREF);
353 #endif /* vref0 */
354
355 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dac0), nxp_lpdac, okay)
356 #if defined(CONFIG_SOC_LPC55S36)
357 CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1U, true);
358 CLOCK_AttachClk(kMAIN_CLK_to_DAC0);
359
360 /* Disable DAC0 power down */
361 POWER_DisablePD(kPDRUNCFG_PD_DAC0);
362 #endif /* SOC platform */
363 #endif /* DAC */
364
365 }
366
367 /**
368 *
369 * @brief Perform basic hardware initialization
370 *
371 * Initialize the interrupt controller device drivers.
372 * Also initialize the timer device driver, if required.
373 *
374 * @return 0
375 */
376
nxp_lpc55xxx_init(void)377 static int nxp_lpc55xxx_init(void)
378 {
379 z_arm_clear_faults();
380
381 /* Initialize FRO/system clock to 96 MHz */
382 clock_init();
383
384 #ifdef CONFIG_GPIO_MCUX_LPC
385 /* Turn on PINT device*/
386 PINT_Init(PINT);
387 #endif
388
389 return 0;
390 }
391
392 #ifdef CONFIG_SOC_RESET_HOOK
393
soc_reset_hook(void)394 void soc_reset_hook(void)
395 {
396 SystemInit();
397
398
399 #ifndef CONFIG_LOG_BACKEND_SWO
400 /*
401 * SystemInit unconditionally enables the trace clock.
402 * Disable the trace clock unless SWO is used
403 */
404 SYSCON->TRACECLKDIV = 0x4000000;
405 #endif
406 }
407
408 #endif /* CONFIG_SOC_RESET_HOOK */
409
410 SYS_INIT(nxp_lpc55xxx_init, PRE_KERNEL_1, 0);
411
412 #if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC55S69_CPU0)
413 /**
414 *
415 * @brief Second Core Init
416 *
417 * This routine boots the secondary core
418 *
419 * @retval 0 on success.
420 *
421 */
422 /* This function is also called at deep sleep resume. */
_second_core_init(void)423 int _second_core_init(void)
424 {
425 int32_t temp;
426
427
428 /* Setup the reset handler pointer (PC) and stack pointer value.
429 * This is used once the second core runs its startup code.
430 * The second core first boots from flash (address 0x00000000)
431 * and then detects its identity (Core no. 1, second) and checks
432 * registers CPBOOT and use them to continue the boot process.
433 * Make sure the startup code for the first core is
434 * appropriate and shareable with the second core!
435 */
436 SYSCON->CPUCFG |= SYSCON_CPUCFG_CPU1ENABLE_MASK;
437
438 /* Boot source for Core 1 from flash */
439 SYSCON->CPBOOT = SYSCON_CPBOOT_CPBOOT(DT_REG_ADDR(
440 DT_CHOSEN(zephyr_code_cpu1_partition)));
441
442 temp = SYSCON->CPUCTRL;
443 temp |= 0xc0c48000;
444 SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CPU1RSTEN_MASK |
445 SYSCON_CPUCTRL_CPU1CLKEN_MASK;
446 SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CPU1CLKEN_MASK) &
447 (~SYSCON_CPUCTRL_CPU1RSTEN_MASK);
448
449 return 0;
450 }
451
452 SYS_INIT(_second_core_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
453
454 #endif /*defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC55S69_CPU0)*/
455
