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/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <8000000>;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
30 #clock-cells = <0>;
31 compatible = "fixed-factor-clock";
38 #clock-cells = <0>;
39 compatible = "fixed-factor-clock";
46 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-lfclk.yaml5 nRF LFCLK (Low Frequency CLocK)
7 The LFCLK can use the following clocks as clock sources:
9 - HFXO: The HFXO clock is used as a clock source if the
10 LFCLK SYNTH mode is selected and the LFXO clock is not
11 available. The HFXO clock is used indirectly through
12 the FLL16M clock in BYPASS mode.
14 - LFXO: The LFXO clock is used as a clock source if the
15 LFCLK SYNTH mode is selected and the LFXO clock is
16 available. The LFXO clock is used indirectly through
17 the FLL16M clock in BYPASS mode.
[all …]
Dst,stm32-rcc.yaml5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
27 Specifying a gated clock:
29 To specify a gated clock, a peripheral should define a "clocks" property encoded
38 control the peripheral clock in that bus register.
[all …]
Dlitex,clkout.yaml7 LiteX Mixed Mode Clock Manager clock output binding
13 "#clock-cells":
17 Number of cells in a clock specifier;
18 Typically 0 for nodes with a single clock output
19 and 1 for nodes with multiple clock outputs.
22 clock-output-names:
26 string of clock output signal name.
28 litex,clock-frequency:
32 default frequency in Hz for clock output
34 litex,clock-phase:
[all …]
Dst,stm32wba-rcc.yaml5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
28 Specifying a gated clock:
30 To specify a gated clock, a peripheral should define a "clocks" property encoded
39 control the peripheral clock in that bus register.
[all …]
Dst,stm32wb0-rcc.yaml5 STM32WB0 Reset and Clock controller node for STM32WB0 devices
6 This node is in charge of the system clock ('SYSCLK') source
11 include: [clock-controller.yaml, base.yaml]
17 "#clock-cells":
20 clock-frequency:
24 default frequency in Hz for clock output
26 slow-clock:
29 Slow clock source selection.
30 On STM32WB0, all slow clock devices are clocked from the same
31 slow clock source, which is selected by this property.
[all …]
Dpwm-clock.yaml5 An external clock signal driven by a PWM pin.
7 The devicetree must define a clock node:
11 compatible = "pwm-clock";
12 #clock-cells = <1>;
16 This will create a device node with a clock-controller
18 clock signals at 1MHz. Note that the PWM_HZ() macro converts the
20 errors if the clock frequency is not an integer number of nanoseconds.
21 The clock frequency can be explicitly set using the clock-frequency
28 compatible: "pwm-clock"
30 include: [clock-controller.yaml, base.yaml]
[all …]
Dnordic,nrf-fll16m.yaml7 The FLL16M can use the following clocks as clock sources:
9 - HFXO: The HFXO clock is used as a clock source if the
11 closed-loop and the LFXO clock is not available.
13 - LFXO: The LFXO clock is used as a clock source if the
14 FLL16M mode is closed-loop and the LFXO clock is
23 clock-names = "hfxo", "lfxo";
28 include: fixed-clock.yaml
31 clock-frequency:
36 description: Clock accuracy in parts per million if open-loop clock source is used.
41 Base clock accuracy in parts per million if closed-loop clock source is used.
Dnordic,nrf-hsfll-global.yaml5 Nordic Global HSFLL clock.
7 The lowest supported clock frequency is the default
8 clock frequency.
15 #clock-cells = <0>;
16 clock-frequency = <320000000>;
17 supported-clock-frequencies = <64000000
27 - "clock-controller.yaml"
33 "#clock-cells":
36 supported-clock-frequencies:
38 description: Supported clock frequencies in ascending order
[all …]
Dfixed-factor-clock.yaml4 description: Generic fixed factor clock provider
6 compatible: "fixed-factor-clock"
8 include: clock-controller.yaml
11 clock-div:
13 description: fixed clock divider
15 clock-mult:
17 description: fixed clock multiplier
21 description: input clock source
23 "#clock-cells":
Dst,stm32g0-pll-clock.yaml7 It can take one of clk_hse or clk_hsi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to I2S
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32g0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
[all …]
Dmicrochip,xec-pcr.yaml4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
28 description: 32 KHz clock source for PLL
33 description: 32 KHz clock source for peripherals
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
[all …]
/Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/
Dsystem_clocks.dtsi13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <48000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <8000000>;
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <96000000>;
37 #clock-cells = <0>;
[all …]
/Zephyr-latest/drivers/timer/
DKconfig.nrf_xrtc8 prompt "Clock startup policy"
14 System clock source is initiated but does not wait for clock readiness.
15 When this option is picked, system clock may not be ready when code relying
22 System clock source initialization waits until clock is available. In some
23 systems, clock initially runs from less accurate source which has faster
24 startup time and then seamlessly switches to the target clock source when
25 it is ready. When this option is picked, system clock is available after
26 system clock driver initialization but it may be less accurate. Option is
27 equivalent to waiting for stability if clock source does not have
33 System clock source initialization waits until clock is stable. When this
[all …]
/Zephyr-latest/dts/bindings/usb/uac2/
Dzephyr,uac2-clock-source.yaml4 description: USB Audio Class 2 Clock Source entity
6 compatible: "zephyr,uac2-clock-source"
9 clock-type:
13 Clock Type indicating whether the Clock Source represents an external
14 clock or an internal clock with either fixed frequency, variable
25 True if clock is synchronized to USB Start of Frame. False if clock is
26 free running. External clock must be free running.
30 description: Clock Frequency Control capabilities
37 description: Clock Validity Control capabilities
44 Input or Output Terminal associated with this Clock Source. Set if clock
[all …]
/Zephyr-latest/dts/riscv/starfive/
Dstarfive_jh7100_clk.dtsi9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <125000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <125000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <100000000>;
27 #clock-cells = <0>;
[all …]
/Zephyr-latest/soc/nxp/kinetis/k8x/
DKconfig35 int "Freescale K8x core clock divider"
38 This option specifies the divide value for the K8x processor core clock
39 from the system clock.
42 int "Freescale K8x bus clock divider"
45 This option specifies the divide value for the K8x bus clock from the
46 system clock.
49 int "Freescale K8x FlexBus clock divider"
52 This option specifies the divide value for the K8x FlexBus clock from the
53 system clock.
56 int "Freescale K8x flash clock divider"
[all …]
/Zephyr-latest/dts/arm/silabs/
Defr32mg24.dtsi11 #include <dt-bindings/clock/silabs/xg24-clock.h>
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
37 #clock-cells = <0>;
38 compatible = "fixed-factor-clock";
41 clock-div = <1>;
[all …]
Defr32xg23.dtsi11 #include <dt-bindings/clock/silabs/xg23-clock.h>
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
37 #clock-cells = <0>;
38 compatible = "fixed-factor-clock";
41 clock-div = <1>;
[all …]
Defr32mg21.dtsi11 #include <dt-bindings/clock/silabs/xg21-clock.h>
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
31 clock-div = <1>;
34 #clock-cells = <0>;
35 compatible = "fixed-factor-clock";
38 clock-div = <2>;
41 #clock-cells = <0>;
[all …]
Defr32bg2x.dtsi22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
31 clock-div = <1>;
34 #clock-cells = <0>;
35 compatible = "fixed-factor-clock";
38 clock-div = <2>;
41 #clock-cells = <0>;
42 compatible = "fixed-factor-clock";
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
DKconfig.samd2x16 This can then be selected as the main clock reference for the SOC.
22 This can then be selected as the main clock reference for the SOC.
25 bool "External 32.768 kHz clock source"
27 Enable the external 32.768 kHz clock source at startup.
28 This can then be selected as the main clock reference for the SOC.
31 bool "External 32.768 kHz clock is a crystal oscillator"
35 Enable the crystal oscillator (if disabled, expect a clock signal on
39 bool "External 0.4..32 MHz clock source"
41 Enable the external 0.4..32 MHz clock source at startup.
42 This can then be selected as the main clock reference for the SOC.
[all …]
/Zephyr-latest/subsys/net/lib/ptp/
Dclock.h8 * @file clock.h
9 * @brief PTP Clock data structure and interface API
35 /* PTP Clock structure declaration. */
50 * @brief PTP Clock time source.
85 * @brief Function initializing PTP Clock instance.
87 * @return Pointer to the structure representing PTP Clock instance.
99 * @brief Function handling STATE DECISION EVENT for the PTP Clock instance.
104 * @brief Function processing received PTP Management message at the PTP Clock level.
114 * @brief Function synchronizing local PTP Hardware Clock to the remote.
122 * @brief Function updating PTP Clock path delay.
[all …]
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
48 compatible = "raspberrypi,pico-clock";
50 clock-names = "pll_sys";
51 clock-frequency = <125000000>;
52 #clock-cells = <0>;
57 compatible = "raspberrypi,pico-clock";
59 clock-names = "pll_sys";
60 clock-frequency = <125000000>;
61 #clock-cells = <0>;
65 compatible = "raspberrypi,pico-clock";
[all …]
Drp2350.dtsi9 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
44 compatible = "raspberrypi,pico-clock";
46 clock-names = "pll_sys";
47 clock-frequency = <150000000>;
48 #clock-cells = <0>;
53 compatible = "raspberrypi,pico-clock";
55 clock-names = "pll_sys";
56 clock-frequency = <150000000>;
57 #clock-cells = <0>;
61 compatible = "raspberrypi,pico-clock";
[all …]

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