Lines Matching full:clock

4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14   core-clock-div:
17     description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19   slow-clock-div:
22       PWM and TACH clock domain divided down from 48 MHz AHB clock. The
28     description: 32 KHz clock source for PLL
33     description: 32 KHz clock source for peripherals
43       32KHz clock monitor minimum valid 32KHz period in 48MHz units
49       32KHz clock monitor maximum valid 32KHz period in 48MHz units
69       Delay in milliseconds after crystal is enabled and clock monitor is
77       Timeout in milliseconds waiting for PLL to lock to new clock source.
81     description: Bypass clkmon check of crystal or XTAL2 single-ended clock.
90   "#clock-cells":
93 clock-cells: