Lines Matching full:clock

7   It can take one of clk_hse or clk_hsi as input clock, with
9   clock in this acceptable range.
11   PLL can have up to 3 output clocks and for each output clock, the
14     f(PLL_P) = f(VCO clock) / PLLP  --> to I2S
15     f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
16     f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
18       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32g0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27   "#clock-cells":
37         Division factor for PLL input clock
63         PLL division factor for PLLCLK (system clock)