Lines Matching full:clock

5   STM32 Reset and Clock controller node.
6   This node is in charge of system clock ('SYSCLK') source selection and controlling
9   Configuring STM32 Reset and Clock controller node:
11   System clock source should be selected amongst the clock nodes available in "clocks"
13   Core clock frequency should also be defined, using "clock-frequency" property.
15           Core clock frequency  = SYSCLK / AHB prescaler
22            clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
27   Specifying a gated clock:
29   To specify a gated clock, a peripheral should define a "clocks" property encoded
38   control the peripheral clock in that bus register.
39   The gated clock is required when accessing to the peripheral controller is needed
40   (generally for configuring the device). If dual clock domain is not used, it is
43   Specifying a domain clock source:
45   Specifying a domain source clock could be done by adding a clock specifier to the
46   clock property:
53   In this example, I2C1 device is assigned HSI as domain clock source.
54   Domain clock is independent from the bus/gated clock and allows access to the device's
55   register while the gated clock is off. As it doesn't feed the peripheral's controller, it
57   It is peripheral driver's responsibility to query and use clock source information in
60   Since the peripheral subsystem rate is dictated by the clock used for peripheral
61   operation, same clock should be used in calls to `clock_control_get_rate()`
63   Note 1: No additional specifier means gating clock is also the clock source (ie
66   Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
68           what is the reset value of the clock source for each peripheral.
70   Specifying a divided domain clock source:
72   Some peripherals are sourced through fixed clock dividers. For such cases there is
74   frequency divided by 2) is done with following clock property:
83 include: [clock-controller.yaml, base.yaml]
89   "#clock-cells":
92   clock-frequency:
96       default frequency in Hz for clock output
112         AHB prescaler. Defines actual core clock frequency (HCLK)
142       System Clock source to PLL. Once done, prescaler is set back to expected
145 clock-cells: