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/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-hsfll-global.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nordic Global HSFLL clock.
7 The lowest supported clock frequency is the default
8 clock frequency.
13 compatible = "nordic,nrf-hsfll-global";
15 #clock-cells = <0>;
16 clock-frequency = <320000000>;
17 supported-clock-frequencies = <64000000
23 compatible: "nordic,nrf-hsfll-global"
26 - "base.yaml"
[all …]
Dpwm-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 An external clock signal driven by a PWM pin.
7 The devicetree must define a clock node:
11 compatible = "pwm-clock";
12 #clock-cells = <1>;
16 This will create a device node with a clock-controller
18 clock signals at 1MHz. Note that the PWM_HZ() macro converts the
19 frequency to time (nanoseconds units). This may result in rounding
20 errors if the clock frequency is not an integer number of nanoseconds.
21 The clock frequency can be explicitly set using the clock-frequency
[all …]
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WBA RCC (Reset and Clock controller).
7 This node is in charge of system clock ('SYSCLK') source selection and controlling
10 Configuring STM32 Reset and Clock controller node:
12 System clock source should be selected amongst the clock nodes available in "clocks"
14 Core clock frequency should also be defined, using "clock-frequency" property.
16 Core clock frequency = SYSCLK / AHB prescaler
22 ahb-prescaler = <2>;
23 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
24 apb1-presacler = <1>;
[all …]
Drenesas,ra-cgc-pclk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA Clock Control Peripheral Clock
6 compatible: "renesas,ra-cgc-pclk"
8 include: [clock-controller.yaml, base.yaml]
11 clock-frequency:
13 description: clock frequency (Hz)
18 description: Prescale divider to calculate the subclock frequency from the
19 system clock frequency.
21 "#clock-cells":
24 clock-cells:
[all …]
Dst,stm32h7-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32H7 RCC (Reset and Clock controller).
7 This node is in charge of system clock ('SYSCLK') source selection and
8 System Clock Generation.
10 Configuring STM32 Reset and Clock controller node:
12 System clock source should be selected amongst the clock nodes available in "clocks"
14 As part of this node configuration, SYSCLK frequency should also be defined, using
15 "clock-frequency" property.
21 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
30 Confere st,stm32-rcc binding for information about domain clocks configuration.
[all …]
Dst,stm32h7rs-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32H7RS RCC (Reset and Clock controller).
7 This node is in charge of system clock ('SYSCLK') source selection and
8 System Clock Generation.
10 Configuring STM32 Reset and Clock controller node:
12 System clock source should be selected amongst the clock nodes available in "clocks"
14 As part of this node configuration, SYSCLK frequency should also be defined, using
15 "clock-frequency" property.
21 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
30 Confere st,stm32-rcc binding for information about domain clocks configuration.
[all …]
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton, NPCM PCC (Power and Clock Controller) node.
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
[all …]
Dst,stm32-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 RCC (Reset and Clock controller).
7 This node is in charge of system clock ('SYSCLK') source selection and controlling
10 Configuring STM32 Reset and Clock controller node:
12 System clock source should be selected amongst the clock nodes available in "clocks"
14 Core clock frequency should also be defined, using "clock-frequency" property.
16 Core clock frequency = SYSCLK / AHB prescaler
22 ahb-prescaler = <2>;
23 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
24 apb1-prescaler = <1>;
[all …]
Dst,stm32l0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
8 input frequency from 2 to 24 MHz.
10 The desired PLL frequency can be computed with the following formula:
12 f(PLL) = f(VCO clock) / PLLDIV --> PLLCLK (System Clock)
14 with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
16 The PLL output frequency must not exceed 32 MHz.
18 compatible: "st,stm32l0-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23 "#clock-cells":
[all …]
Dst,stm32wb0-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WB0 RCC (Reset and Clock controller).
7 This node is in charge of the system clock ('SYSCLK') source
10 compatible: "st,stm32wb0-rcc"
12 include: [clock-controller.yaml, base.yaml]
18 "#clock-cells":
21 clock-frequency:
25 default frequency in Hz for clock output
27 slow-clock:
30 Slow clock source selection.
[all …]
Dst,stm32wba-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
9 This PLL could take one of clk_hse or clk_hsi as input clock, with
10 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
11 clock in this acceptable range.
13 PLL1 can have up to 3 output clocks and for each output clock, the
14 frequency can be computed with the following formula:
16 f(PLL_P) = f(VCO clock) / PLLP
17 f(PLL_Q) = f(VCO clock) / PLLQ
18 f(PLL_R) = f(VCO clock) / PLLR
20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
[all …]
Dst,stm32n6-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
9 These PLLs can take one of clk_hse, clk_hsi or clk_msi as input clock, with
10 an input frequency from 5 to 50 MHz. PLLM factor is used to set the input
11 clock in this acceptable range.
13 Each PLL has one output clock whose frequency can be computed with the
16 f(PLL_P) = f(VCO clock) / (PLLP1 × PLLP2)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
21 clock output to the lowest frequency.
23 The PLL output frequency must not exceed 3200 MHz.
25 compatible: "st,stm32n6-pll-clock"
[all …]
Dst,stm32wb0-lsi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WB0 LSI Clock
7 The STM32WB0 MCUs are equipped with a regular RC LSI clock with a frequency of 24~40kHz.
8 The SoCs are also equipped with hardware to perform LSI frequency measurement, which
9 allows to adapt all frequency-based calculations to a somewhat accurate value, ensuring
10 that the software does not get too much out of sync with real-world time.
12 Several LSI frequency measurement options can be configured via Kconfig.
14 compatible: "st,stm32wb0-lsi-clock"
16 include: [fixed-clock.yaml]
Dst,stm32u0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
12 frequency can be computed with the following formulae:
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
[all …]
Dst,stm32n6-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32N6 RCC (Reset and Clock controller).
7 This node is in charge of system clock ('SYSCLK') source selection and
8 System Clock Generation.
10 Configuring STM32 Reset and Clock controller node:
12 System clock source should be selected amongst the clock nodes available in "clocks"
14 As part of this node configuration, SYSCLK frequency should also be defined, using
15 "clock-frequency" property.
21 clock-frequency = <DT_FREQ_M(400)>;
22 ahb-prescaler = <2>;
[all …]
/Zephyr-latest/dts/bindings/counter/
Dandestech,atcpit100.yaml4 # SPDX-License-Identifier: Apache-2.0
21 clock-frequency:
24 description: channel clock source
30 The prescaler value defines the counter frequency
31 (clock-frequency/prescaler) in atcpit100 counter driver, the prescaler
32 value could be in range [1 .. clock-frequency] and 1 means no prescaler
33 for the PIT clock-frequency.
35 Defaults to 1 to use the PIT clock-frequency as the counter frequency.
38 larger than a counter tick period, reducing the counter frequency to
42 clock cycles for counter interface, setting prescaler value to 600 in
/Zephyr-latest/dts/bindings/usb/uac2/
Dzephyr,uac2-clock-source.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: USB Audio Class 2 Clock Source entity
6 compatible: "zephyr,uac2-clock-source"
9 clock-type:
13 Clock Type indicating whether the Clock Source represents an external
14 clock or an internal clock with either fixed frequency, variable
15 frequency, or programmable frequency.
17 - "external"
18 - "internal-fixed"
19 - "internal-variable"
[all …]
/Zephyr-latest/dts/riscv/starfive/
Dstarfive_jh7100_clk.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <125000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <125000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <100000000>;
[all …]
/Zephyr-latest/dts/bindings/timer/
Dnuclei,systimer.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Nuclei system timer provides RISC-V privileged mtime and mtimecmp
12 include: "riscv,machine-timer.yaml"
15 clk-divider:
18 clk-divider specifies the division ratio to the CPU frequency that
19 clock used by the system timer.
21 different clock sources.
24 For example, the CPU clock frequency is 108MHz, and the system timer
25 uses 27MHz, which is the CPU clock divided by 4.
26 In this case, the CPU clock frequency is defined in the CPU node
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2l1xxxxfp.dtsi3 * Copyright (c) 2024-2025 Renesas Electronics Corporation
7 * SPDX-License-Identifier: Apache-2.0
13 #address-cells = <1>;
14 #size-cells = <1>;
16 xtal: clock-main-osc {
17 compatible = "renesas,ra-cgc-external-clock";
18 clock-frequency = <DT_FREQ_M(20)>;
19 #clock-cells = <0>;
23 hoco: clock-hoco {
24 compatible = "fixed-clock";
[all …]
/Zephyr-latest/drivers/clock_control/
DKconfig.stm321 # STM32 MCU clock control driver config
5 # SPDX-License-Identifier: Apache-2.0
8 bool "STM32 Reset & Clock Control"
16 $(dt_nodelabel_has_prop,clk_hse,css-enabled))
18 Enable driver for Reset & Clock Control subsystem found
24 DT_STM32_HSE_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_HSE_CLOCK),clock-frequency)
27 int "HSE clock value"
31 Value of external high-speed clock (HSE). This symbol could be optionally
32 configured using device tree by setting "clock-frequency" value of clk_hse
36 clock-frequency = <DT_FREQ_M(25)>;
[all …]
DKconfig.nrf1 # Clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
11 of the clock control driver.
14 bool "NRF Clock controller support"
20 Enable support for the Nordic Semiconductor nRFxx series SoC clock
30 prompt "32KHz clock source"
58 bool "LF clock calibration"
62 If calibration is disabled when RC is used for low frequency clock then
63 accuracy of the low frequency clock will degrade. Disable on your own
74 Enabling indicates that calibration is performed by the clock control driver.
[all …]
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dadsp_clk.h4 * SPDX-License-Identifier: Apache-2.0
20 /** @brief Set cAVS clock frequency
22 * Set xtensa core clock speed.
24 * @param freq Clock frequency index to be set
26 * @return 0 on success, -EINVAL if freq_idx is not valid
30 /** @brief Get list of cAVS clock information
32 * Returns an array of clock information, one for each core.
34 * @return array with clock information
65 /* Clock sources used by dai */
81 uint32_t frequency; member
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/Zephyr-latest/subsys/logging/backends/
DKconfig.swo2 # SPDX-License-Identifier: Apache-2.0
14 int "SWO reference clock frequency"
15 …default $(dt_node_int_prop_int,$(dt_nodelabel_path,itm),swo-ref-frequency) if $(dt_nodelabel_enabl…
16 …default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if $(dt_node_has_prop,/cpus/cpu@0,cloc…
19 Set SWO reference frequency. In most cases it is equal to CPU
20 frequency.
23 int "Set SWO output frequency"
26 Set SWO output frequency. Value 0 will select maximum frequency
28 frequency SWO operation. In this case the frequency has to be set
32 viewer programs will configure SWO frequency when attached to the
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/Zephyr-latest/samples/boards/nordic/clock_control/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 int "Frequency specification to request from clock in Hz"
8 0 -> ignore frequency
9 >0 -> use at minimum selected frequency. To select the
10 highest supported frequency use UINT32_MAX.
13 int "Accuracy specification to request from clock in PPM"
16 0 -> ignore accuracy
17 1 -> use max accuracy
18 >1 -> use at minimum selected accuracy
21 int "Precision specification to request from clock"
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