Lines Matching +full:clock +full:- +full:frequency

2  * Copyright (c) 2022-2024, Intel Corporation.
4  * SPDX-License-Identifier: Apache-2.0
17 /* Extract reference clock from platform clock source */
31 	 * Based on the clock source, read the values from System Manager boot  in get_ref_clk()
33 	 * hand-off data.  in get_ref_clk()
50 		__ASSERT(0, "Invalid input clock source");  in get_ref_clk()
54 	/* Get reference clock divider */  in get_ref_clk()
56 	__ASSERT(arefclkdiv != 0, "Reference clock divider is zero");  in get_ref_clk()
59 	/* Feedback clock divider */  in get_ref_clk()
68 /* Calculate clock frequency based on parameter */
77 	 * Select source for the active 5:1 clock selection when the PLL  in get_clk_freq()
85 		__ASSERT(pllcx_div != 0, "Main PLLC clock divider is zero");  in get_clk_freq()
92 		__ASSERT(pllcx_div != 0, "Peripheral PLLC clock divider is zero");  in get_clk_freq()
109 		__ASSERT(0, "Invalid clock source select");  in get_clk_freq()
113 	LOG_DBG("%s: clock source %lu and its value %u\n",  in get_clk_freq()
119 /* Get L3 free clock */
127 /* Get L4 mp clock */
140  * Get L4 sp clock.
155 /* Get MPU clock */
158 	uint8_t cpu_id = arch_curr_cpu()->id;  in get_mpu_clk()
190 	/* Division setting for ping pong counter in clock slice */  in get_mpu_clk()
196 /* Calculate clock frequency to be used for watchdog timer */
207 /* Get clock frequency to be used for UART driver */
213 /* Calculate clock frequency to be used for SDMMC driver */
223 /* Calculate clock frequency to be used for Timer driver */
229 /* Calculate clock frequency to be used for QSPI driver */
238 	 * In ATF, the qspi clock is divided by 1000 and loaded in scratch cold register 0  in get_qspi_clk()
239 	 * So in Zephyr, reverting back the clock frequency by multiplying by 1000.  in get_qspi_clk()
244 /* Calculate clock frequency to be used for I2C driver */
250 /* Calculate clock frequency to be used for I3C driver */