Lines Matching +full:clock +full:- +full:frequency

2 # SPDX-License-Identifier: Apache-2.0
9   This PLL could take one of clk_hse or clk_hsi as input clock, with
10   an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
11   clock in this acceptable range.
13   PLL1 can have up to 3 output clocks and for each output clock, the
14   frequency can be computed with the following formula:
16     f(PLL_P) = f(VCO clock) / PLLP
17     f(PLL_Q) = f(VCO clock) / PLLQ
18     f(PLL_R) = f(VCO clock) / PLLR
20       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22   Note: VCOx frequency range is 128 to 544 MHz. To reduce the power consumption,
23         it is recommended to configure the VCO to the lowest frequency.
25   The PLL output frequency must not exceed 100 MHz.
27 compatible: "st,stm32wba-pll-clock"
29 include: [clock-controller.yaml, base.yaml]
33   "#clock-cells":
39   div-m:
44         input clock
45         Valid range: 1 - 8
47   mul-n:
52         Valid range: 4 - 512
54   div-q:
58         Valid range: 1 - 128
60   div-r:
65         Valid range: 1 - 128