Lines Matching +full:clock +full:- +full:frequency
2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7 devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 As part of this node configuration, SYSCLK frequency should also be defined, using
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
46 default frequency in Hz for clock output
52 - 1
54 D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
55 lower than SYSCLK frequency (actual core frequency).
58 use them independently in Zephyr clock subsystem.
64 D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
66 - 1
67 - 2
68 - 4
69 - 8
70 - 16
71 - 64
72 - 128
73 - 256
74 - 512
82 - 1
83 - 2
84 - 4
85 - 8
86 - 16
94 - 1
95 - 2
96 - 4
97 - 8
98 - 16
106 - 1
107 - 2
108 - 4
109 - 8
110 - 16
118 - 1
119 - 2
120 - 4
121 - 8
122 - 16
124 clock-cells:
125 - bus
126 - bits