Lines Matching +full:clock +full:- +full:frequency
2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7RS devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 As part of this node configuration, SYSCLK frequency should also be defined, using
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7rs-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
46 default frequency in Hz for clock output
52 - 1
53 - 2
54 - 4
55 - 8
56 - 16
57 - 64
58 - 128
59 - 256
60 - 512
62 CPU clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
63 lower than SYSCLK frequency (actual core frequency).
66 use them independently in Zephyr clock subsystem.
72 peripheral clock to the Bus Matrix APB (1/2/4/5) and AHB(1/2/3/4/5) peripheral
73 divider of the CPU clock by this prescaler (BMPRE register)
75 - 1
76 - 2
77 - 4
78 - 8
79 - 16
80 - 64
81 - 128
82 - 256
83 - 512
91 - 1
92 - 2
93 - 4
94 - 8
95 - 16
103 - 1
104 - 2
105 - 4
106 - 8
107 - 16
115 - 1
116 - 2
117 - 4
118 - 8
119 - 16
127 - 1
128 - 2
129 - 4
130 - 8
131 - 16
133 clock-cells:
134 - bus
135 - bits