| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_npcm.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcm_clock.h>
25 * Core Domain Clock Generator (CDCG) device registers
28 /* High Frequency Clock Generator (HFCG) registers */
44 /* 0x010: HFCG Bus Clock Dividers */
47 /* 0x012: HFCG Bus Clock Dividers */
50 /* 0x014: HFCG Bus Clock Dividers */
53 /* 0x01d: HFCG Bus Clock Dividers */
57 /* clock bus references */
72 /* clock enable/disable references */
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| D | Kconfig.npcx | 1 # NPCX Clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "NPCX clock controller driver"
11 Enable support for NPCX clock controller driver.
16 bool "Generate LFCLK by on-chip Crystal Oscillator"
18 When this option is enabled, the internal 32.768 KHz clock (LFCLK)
19 is generated by the on-chip Crystal Oscillator (XTOSC).
20 This includes an on-chip oscillator, to which an external crystal
24 bool "Indicates that the clock controller supports APB4 bus"
27 Selected if NPCX series supports APB4 bus.
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| /Zephyr-latest/dts/bindings/misc/ |
| D | nxp,s32-emios.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 as a reference timebase (master bus) for other channels.
10 compatible: "nxp,s32-emios"
21 interrupt-names:
27 clock-divider:
31 Clock divider value for the global prescaler. Could be in range [1 ... 256]
33 internal-cnt:
39 child-binding:
40 child-binding:
42 Node for eMIOS master bus. Each channel is capable to become a master bus has
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,ftm-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,ftm-pwm"
8 include: [pwm-controller.yaml, "nxp,ftm.yaml", "pinctrl-device.yaml"]
11 "#pwm-cells":
14 pinctrl-0:
17 clock-source:
21 - "system"
22 - "fixed"
23 - "external"
25 Select one of three possible clock sources for the FTM counter:
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| D | nxp,s32-emios-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 require to use a reference timebase from a master bus.
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
28 master-bus = <&emios1_bus_a>;
29 pwm-mode = "OPWMB";
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
7 clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
16 Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
21 ahb-prescaler = <2>;
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| D | st,stm32wba-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
7 clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
16 Last, peripheral bus clocks (typically PCLK1, PCLK2, PCLK7) should be configured using
21 ahb-prescaler = <2>;
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| D | st,stm32h7rs-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7RS devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
14 "clock-frequency" property.
15 Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
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| D | nuvoton,npcx-pcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton, NPCX PCC (Power and Clock Controller) node.
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
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| D | st,stm32h7-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7 devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
14 "clock-frequency" property.
15 Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
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| D | nuvoton,npcm-pcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton, NPCM PCC (Power and Clock Controller) node.
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
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| /Zephyr-latest/dts/bindings/video/ |
| D | video-interfaces.yaml | 2 # SPDX-License-Identifier: Apache-2.0
13 bus, an 'endpoint' child node must be provided for each of them. If more than one
16 scheme using '#address-cells', '#size-cells' and 'reg' properties is used.
19 specify #address-cells, #size-cells properties independently for the 'port' and
25 #address-cells = <1>;
26 #size-cells = <0>;
37 Two 'endpoint' nodes must be linked with each other via their 'remote-endpoint'
39 references are currently not possible. A 'remote-endpoint-label' string is used
40 instead to be able to specify, at least, the label of the peer remote-endpoint.
44 compatible = "zephyr,video-interfaces";
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_sdmmc.c | 4 * SPDX-License-Identifier: Apache-2.0
20 #warning "Missing clock 48MHz"
24 #warning "Missing clock I2S PLL clock"
37 /* Test clock_on(gating clock) */ in ZTEST()
40 zassert_true((r == 0), "Could not enable SDMMC gating clock"); in ZTEST()
42 zassert_true(__HAL_RCC_SDIO_IS_CLK_ENABLED(), "SDMMC gating clock should be on"); in ZTEST()
43 TC_PRINT("SDMMC gating clock on\n"); in ZTEST()
45 zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(sdmmc1)) > 1), "No domain clock defined in dts"); in ZTEST()
47 if (pclken[1].bus == STM32_SRC_CK48) { in ZTEST()
48 /* CLK 48 is enabled through the clock-mux */ in ZTEST()
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32_common_clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
9 /** System clock */
20 /** Clock divider */
21 #define STM32_CLOCK_DIV(div) (((div) - 1) << STM32_CLOCK_DIV_SHIFT)
39 * @param val Clock configuration field value (0~0x1F)
54 * Pack RCC clock register offset and bit in two 32-bit values
57 * @param bus STM32 bus name (expands to STM32_CLOCK_BUS_{bus})
58 * @param bit Clock bit
60 #define STM32_CLOCK(bus, bit) (STM32_CLOCK_BUS_##bus) (1 << bit) argument
|
| /Zephyr-latest/soc/nxp/kinetis/k8x/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
35 int "Freescale K8x core clock divider"
38 This option specifies the divide value for the K8x processor core clock
39 from the system clock.
42 int "Freescale K8x bus clock divider"
45 This option specifies the divide value for the K8x bus clock from the
46 system clock.
49 int "Freescale K8x FlexBus clock divider"
52 This option specifies the divide value for the K8x FlexBus clock from the
53 system clock.
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| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | arm_clock_control.h | 4 * SPDX-License-Identifier: Apache-2.0
15 * @brief Clock subsystem IDs for ARM family SoCs
18 /* CMSDK BUS Mapping */
32 /* ARM family SoCs supported Bus types */
33 enum arm_bus_type_t bus; member
34 /* Clock can be configured for 3 states: Active, Sleep, Deep Sleep */
36 /* Identifies the device on the bus */
|
| /Zephyr-latest/drivers/ethernet/ |
| D | eth_dwmac_stm32h7x.c | 6 * SPDX-License-Identifier: Apache-2.0
17 /* be compatible with the HAL-based driver here */
36 .bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
40 .bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
44 .bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bus),
53 p->clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in dwmac_bus_init()
55 if (!device_is_ready(p->clock)) { in dwmac_bus_init()
56 LOG_ERR("clock control device not ready"); in dwmac_bus_init()
57 return -ENODEV; in dwmac_bus_init()
60 ret = clock_control_on(p->clock, (clock_control_subsys_t)&pclken); in dwmac_bus_init()
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | st,stm32-i2c-v2.yaml | 1 # Copyright (c) 2017 I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-i2c-v2"
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
26 An optional table of pre-computed i2c timing values with the
27 matching clock configuration.
29 Precise timings values for a given Hardware can be pre-computed
33 Because timing value is valid for a given I2C peripheral clock
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| /Zephyr-latest/dts/bindings/test/ |
| D | vnd,clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Test Clock Controller
6 compatible: "vnd,clock"
8 include: [clock-controller.yaml, base.yaml]
11 "#clock-cells":
14 clock-cells:
15 - bus
16 - bits
|
| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | renesas,smartbond-nor-psram.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
59 erase-cs-idle-min-ns:
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| /Zephyr-latest/doc/hardware/peripherals/ |
| D | i2c.rst | 3 Inter-Integrated Circuit (I2C) Bus
12 `NXP I2C Bus Specification Rev 7.0 <i2c-specification_>`_. These changed
15 `I2C`_ (Inter-Integrated Circuit, pronounced "eye
16 squared see") is a commonly-used two-signal shared peripheral interface
17 bus. Many system-on-chip solutions provide controllers that communicate
18 on an I2C bus. Devices on the bus can operate in two roles: as a
19 "controller" that initiates transactions and controls the clock, or as a
24 .. _i2c-controller-api:
29 Zephyr's I2C controller API is used when an I2C peripheral controls the bus,
30 particularly the start and stop conditions and the clock. This is
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | mikro-bus.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on Mikro BUS headers.
7 The Mikro BUS layout provides two headers, aligned on the opposite
12 … https://download.mikroe.com/documents/standards/mikrobus/mikrobus-standard-specification-v200.pdf
15 numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
16 (PWM - SDA). The bottom 2 pins on each side are used for input voltage
19 Analog - AN PWM - PWM output
20 Reset - RST INT - Hardware Interrupt
21 SPI Chip Select - CS RX - UART Receive
22 SPI Clock - SCK TX - UART Transmit
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| /Zephyr-latest/dts/bindings/i3c/ |
| D | nuvoton,npcx-i3c.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 /* If CONFIG_I3C_NPCX is enabled, the suggested clock configuration is as follows: */
11 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
12 core-prescaler = <3>; /* CORE_CLK runs at 30MHz */
13 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
14 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
15 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
26 /* I3C clock frequency suggestion = <PP_SCL, OD_SCL> */
30 i3c-scl-hz = <12500000>;
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| /Zephyr-latest/dts/bindings/mipi-dsi/ |
| D | mipi-dsi-host.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI-DSI hosts
8 bus: mipi-dsi
11 "#address-cells":
15 "#size-cells":
19 phy-clock:
22 MIPI PHY clock frequency. Should be set to ensure clock frequency is at
23 least (pixel clock * bits per output pixel) / number of mipi data lanes
|
| /Zephyr-latest/drivers/w1/ |
| D | w1_max32.c | 2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
22 const struct device *clock; member
37 const struct max32_w1_config *const cfg = dev->config; in api_reset_bus()
38 mxc_owm_regs_t *regs = cfg->regs; in api_reset_bus()
40 /* 0 if no 1-wire devices responded during the presence pulse, 1 otherwise */ in api_reset_bus()
44 if (regs->ctrl_stat & MXC_F_OWM_CTRL_STAT_OW_INPUT) { in api_reset_bus()
61 /* if no slave connected to the bus, read bits shall be logical ones */ in api_read_bit()
64 return -EIO; in api_read_bit()
78 /* if no slave connected to the bus, write shall success */ in api_write_bit()
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