1 /*
2 * Copyright (c) 2023-2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/drivers/w1.h>
8 #include <zephyr/logging/log.h>
9 #include <zephyr/drivers/pinctrl.h>
10 #include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
11
12 #include <wrap_max32_owm.h>
13
14 #define DT_DRV_COMPAT adi_max32_w1
15
16 LOG_MODULE_REGISTER(w1_max32, CONFIG_W1_LOG_LEVEL);
17
18 struct max32_w1_config {
19 struct w1_master_config w1_config;
20 mxc_owm_regs_t *regs;
21 const struct pinctrl_dev_config *pctrl;
22 const struct device *clock;
23 struct max32_perclk perclk;
24 uint8_t internal_pullup;
25 uint8_t external_pullup;
26 uint8_t long_line_mode;
27 };
28
29 struct max32_w1_data {
30 struct w1_master_data w1_data;
31 uint8_t reg_device_config;
32 };
33
api_reset_bus(const struct device * dev)34 static int api_reset_bus(const struct device *dev)
35 {
36 int ret;
37 const struct max32_w1_config *const cfg = dev->config;
38 mxc_owm_regs_t *regs = cfg->regs;
39
40 /* 0 if no 1-wire devices responded during the presence pulse, 1 otherwise */
41 ret = MXC_OWM_Reset();
42 if (ret > 0) {
43 /* Check OW pin input state due to presence detect pin seems not work well */
44 if (regs->ctrl_stat & MXC_F_OWM_CTRL_STAT_OW_INPUT) {
45 ret = 1; /* At least 1 device on the line */
46 } else {
47 ret = 0; /* no device on the line */
48 }
49 }
50
51 return ret;
52 }
53
api_read_bit(const struct device * dev)54 static int api_read_bit(const struct device *dev)
55 {
56 int ret;
57
58 ret = MXC_OWM_ReadBit();
59 if (ret < 0) {
60 if (MXC_OWM_GetPresenceDetect() == 0) {
61 /* if no slave connected to the bus, read bits shall be logical ones */
62 ret = 1;
63 } else {
64 return -EIO;
65 }
66 }
67
68 return ret;
69 }
70
api_write_bit(const struct device * dev,bool bit)71 static int api_write_bit(const struct device *dev, bool bit)
72 {
73 int ret;
74
75 ret = MXC_OWM_WriteBit(bit);
76 if (ret < 0) {
77 if (MXC_OWM_GetPresenceDetect() == 0) {
78 /* if no slave connected to the bus, write shall success */
79 ret = 0;
80 } else {
81 return -EIO;
82 }
83 }
84
85 return ret;
86 }
87
api_read_byte(const struct device * dev)88 static int api_read_byte(const struct device *dev)
89 {
90 int ret;
91
92 ret = MXC_OWM_ReadByte();
93 if (ret < 0) {
94 if (MXC_OWM_GetPresenceDetect() == 0) {
95 /* if no slave connected to the bus, read bits shall be logical ones */
96 ret = 0xff;
97 } else {
98 return -EIO;
99 }
100 }
101
102 return ret;
103 }
104
api_write_byte(const struct device * dev,uint8_t byte)105 static int api_write_byte(const struct device *dev, uint8_t byte)
106 {
107 int ret;
108
109 ret = MXC_OWM_WriteByte(byte);
110 if (ret < 0) {
111 if (MXC_OWM_GetPresenceDetect() == 0) {
112 /* if no slave connected to the bus, write shall success */
113 ret = 0;
114 } else {
115 return -EIO;
116 }
117 }
118
119 return ret;
120 }
121
api_configure(const struct device * dev,enum w1_settings_type type,uint32_t value)122 static int api_configure(const struct device *dev, enum w1_settings_type type, uint32_t value)
123 {
124 int ret = 0;
125
126 switch (type) {
127 case W1_SETTING_SPEED:
128 MXC_OWM_SetOverdrive(value);
129 break;
130 case W1_SETTING_STRONG_PULLUP:
131 const struct max32_w1_config *const dev_config = dev->config;
132 mxc_owm_regs_t *regs = dev_config->regs;
133
134 if (value == 1) {
135 regs->cfg |= MXC_F_OWM_CFG_EXT_PULLUP_MODE;
136 } else {
137 regs->cfg &= ~MXC_F_OWM_CFG_EXT_PULLUP_MODE;
138 }
139 break;
140 default:
141 return -EINVAL;
142 }
143
144 return ret;
145 }
146
w1_max32_init(const struct device * dev)147 static int w1_max32_init(const struct device *dev)
148 {
149 int ret;
150 const struct max32_w1_config *const cfg = dev->config;
151 mxc_owm_cfg_t mxc_owm_cfg;
152
153 if (!device_is_ready(cfg->clock)) {
154 LOG_ERR("clock control device not ready");
155 return -ENODEV;
156 }
157
158 MXC_OWM_Shutdown();
159
160 ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
161 if (ret != 0) {
162 LOG_ERR("cannot enable OWM clock");
163 return ret;
164 }
165
166 ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
167 if (ret) {
168 return ret;
169 }
170
171 mxc_owm_cfg.int_pu_en = cfg->internal_pullup;
172 mxc_owm_cfg.ext_pu_mode = cfg->external_pullup;
173 mxc_owm_cfg.long_line_mode = cfg->long_line_mode;
174
175 ret = Wrap_MXC_OWM_Init(&mxc_owm_cfg);
176
177 return ret;
178 }
179
180 static DEVICE_API(w1, w1_max32_driver_api) = {
181 .reset_bus = api_reset_bus,
182 .read_bit = api_read_bit,
183 .write_bit = api_write_bit,
184 .read_byte = api_read_byte,
185 .write_byte = api_write_byte,
186 .configure = api_configure,
187 };
188
189 #define MAX32_W1_INIT(_num) \
190 PINCTRL_DT_INST_DEFINE(_num); \
191 static const struct max32_w1_config max32_w1_config_##_num = { \
192 .w1_config.slave_count = W1_INST_SLAVE_COUNT(_num), \
193 .regs = (mxc_owm_regs_t *)DT_INST_REG_ADDR(_num), \
194 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
195 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
196 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
197 .perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
198 .internal_pullup = DT_INST_PROP(_num, internal_pullup), \
199 .external_pullup = DT_INST_PROP_OR(_num, external_pullup, 0), \
200 .long_line_mode = DT_INST_PROP(_num, long_line_mode), \
201 }; \
202 static struct max32_w1_data max32_owm_data##_num; \
203 DEVICE_DT_INST_DEFINE(_num, w1_max32_init, NULL, &max32_owm_data##_num, \
204 &max32_w1_config_##_num, POST_KERNEL, CONFIG_W1_INIT_PRIORITY, \
205 &w1_max32_driver_api);
206
207 DT_INST_FOREACH_STATUS_OKAY(MAX32_W1_INIT)
208