Lines Matching +full:clock +full:- +full:bus

2 # SPDX-License-Identifier: Apache-2.0
5   STM32H7 RCC (Reset and Clock controller).
7   This node is in charge of system clock ('SYSCLK') source selection and
8   System Clock Generation.
10   Configuring STM32 Reset and Clock controller node:
12   System clock source should be selected amongst the clock nodes available in "clocks"
15   "clock-frequency" property.
16   Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
21            clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
30   Confere st,stm32-rcc binding for information about domain clocks configuration.
32 compatible: "st,stm32h7-rcc"
34 include: [clock-controller.yaml, base.yaml]
40   "#clock-cells":
43   clock-frequency:
47       default frequency in Hz for clock output
53       - 1
55         D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
59         use them independently in Zephyr clock subsystem.
65         D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
67       - 1
68       - 2
69       - 4
70       - 8
71       - 16
72       - 64
73       - 128
74       - 256
75       - 512
83       - 1
84       - 2
85       - 4
86       - 8
87       - 16
95       - 1
96       - 2
97       - 4
98       - 8
99       - 16
107       - 1
108       - 2
109       - 4
110       - 8
111       - 16
119       - 1
120       - 2
121       - 4
122       - 8
123       - 16
125 clock-cells:
126   - bus
127   - bits