1# Copyright (c) 2023 Renesas Electronics Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4description: Renesas Smartbond(tm) NOR/PSRAM controller
5
6include: base.yaml
7
8compatible: "renesas,smartbond-nor-psram"
9
10properties:
11  reg:
12    required: true
13
14  is-ram:
15    type: boolean
16    description: |
17      If present, the memory controller will be configured to drive PSRAM devices.
18
19  dev-size:
20    type: int
21    required: true
22    description: |
23      Memory size/capacity in bits.
24
25  dev-type:
26    type: int
27    required: true
28    description: |
29      Device type, part of device ID, used to verify the memory device used.
30
31  dev-density:
32    type: int
33    required: true
34    description: |
35      Device density, part of device ID, used to verify the memory device used.
36      [7:0] should reflect the density value itself and [15:8] should reflect
37      the mask that should be applied to the returned device ID value.
38      This is because part of its byte value might contain invalid bits.
39
40  dev-id:
41    type: int
42    required: true
43    description: |
44      Manufacturer ID, part of device ID, used to verify the memory device used.
45
46  reset-delay-us:
47    type: int
48    required: true
49    description: |
50      Time in microseconds (us) the memory device can accept the next command following a SW reset.
51
52  read-cs-idle-min-ns:
53    type: int
54    required: true
55    description: |
56      Min. time, in nanoseconds, the #CS line should remain inactive between
57      the transmission of two different instructions.
58
59  erase-cs-idle-min-ns:
60    type: int
61    description: |
62      Min. time, in nanoseconds, the #CS line should remain inactive after the execution
63      of a write enable, erase, erase suspend or erase resume instruction. This setting
64      is not used if is-ram property is present.
65
66  enter-qpi-cmd:
67    type: int
68    description: |
69      Command to enter the QPI mode supported by a memory device
70      (should be transmitted in single bus mode).
71
72  exit-qpi-cmd:
73    type: int
74    description: |
75      Command to exit the QPI mode supported by a memory device
76      (should be transmitted in quad bus mode).
77
78  enter-qpi-mode:
79    type: boolean
80    description: |
81      If present, the memory device will enter the QPI mode which typically reflects that
82      all bytes be sent in quad bus mode. It's a pre-requisite that read and write
83      commands, that should be read-cmd and write-cmd respectively, reflect the QPI mode.
84
85  read-cmd:
86    type: int
87    default: 0x03
88    description: |
89      Read command for single/burst read accesses in auto mode. Default value is the opcode
90      for single mode which is supported by all memory devices.
91
92  write-cmd:
93    type: int
94    default: 0x02
95    description: |
96      Write command for single/burst write accesses in auto mode. Default value is the opcode
97      for single mode which is supported by all memory devices.
98
99  clock-mode:
100    type: string
101    enum:
102      - "spi-mode0"
103      - "spi-mode3"
104    default: "spi-mode0"
105    description: |
106      Clock mode when #CS is idle/inactive
107
108      - Mode0: #CLK is low when #CS is inactive
109      - Mode3: #CLK is high when #CS is inactive
110
111      Mode0 is selected by default as it should be supported by all memory devices.
112
113  addr-range:
114    type: string
115    enum:
116      - "addr-range-24bit"
117      - "addr-range-32bit"
118    default: "addr-range-24bit"
119    description: |
120      Address size to use in auto mode. In 24-bit mode up to 16MB can be
121      accessed whilst in 32-bit mode up to 32MB can be accessed which is
122      the max. address space supported by QSPICx. Default value is 24-bit
123      mode which is supported by all memory devices.
124
125  clock-div:
126    type: int
127    description: |
128      Clock divider for QSPIC2 controller. The clock path of
129      this block is always DIV1 which reflects the current
130      system clock.
131
132  tcem-max-us:
133    type: int
134    description: |
135      If a non zero value is applied, then Tcem should be taken into
136      consideration by QSPIC2 so that it can split a burst read/write
137      access in case the total time exceeds the defined value
138      (at the cost of extra cycles required for re-sending the instruction,
139      address and dummy bytes, if any). This setting is meaningful only if
140      is-ram is present. This value reflects the max. time in microseconds
141      the #CS line can be driven low in a write/read burst access
142      (required for the auto-refresh mechanism, when supported).
143
144  dummy-bytes-count:
145    type: string
146    required: true
147    enum:
148      - "dummy-bytes-count0"
149      - "dummy-bytes-count1"
150      - "dummy-bytes-count2"
151      - "dummy-bytes-count4"
152    description: |
153      Number of dummy bytes to send for single/burst read access in auto mode.
154
155  extra-byte-enable:
156    type: boolean
157    description: |
158      If present, the extra byte will be sent after the dummy bytes, if any.
159      This should be useful if 3 dummy bytes are required. In such a case,
160      dummy-bytes-count should be set to 2.
161
162  extra-byte:
163    type: int
164    description: |
165      Extra byte to be sent, if extra-byte-enable is present.
166
167  rx-addr-mode:
168    type: string
169    enum:
170      - "single-spi"
171      - "dual-spi"
172      - "quad-spi"
173    default: "single-spi"
174    description: |
175      Describes the mode of SPI bus during the address phase for single/burst
176      read accesses in auto mode. Default value is single mode which should be
177      supported by all memory devices.
178
179  rx-inst-mode:
180    type: string
181    enum:
182      - "single-spi"
183      - "dual-spi"
184      - "quad-spi"
185    default: "single-spi"
186    description: |
187      Describes the mode of SPI bus during the instruction phase for single/burst
188      read accesses in auto mode. Default value is single mode which should be
189      supported by all memory devices.
190
191  rx-data-mode:
192    type: string
193    enum:
194      - "single-spi"
195      - "dual-spi"
196      - "quad-spi"
197    default: "single-spi"
198    description: |
199      Describes the mode of SPI bus during the data phase for single/burst
200      read accesses in auto mode. Default value is single mode which should
201      be supported by all memory devices.
202
203  rx-dummy-mode:
204    type: string
205    enum:
206      - "single-spi"
207      - "dual-spi"
208      - "quad-spi"
209    default: "single-spi"
210    description: |
211      Describes the mode of SPI bus during the dummy bytes phase for single/burst
212      read accesses in auto mode. The single mode should be supported by all
213      memory devices.
214
215  rx-extra-mode:
216    type: string
217    enum:
218      - "single-spi"
219      - "dual-spi"
220      - "quad-spi"
221    description: |
222      Describes the mode of SPI bus during the extra byte phase for single/burst
223      read accesses in auto mode. Default value is single mode which should be
224      supported by all memory devices.
225
226  tx-addr-mode:
227    type: string
228    enum:
229      - "single-spi"
230      - "dual-spi"
231      - "quad-spi"
232    default: "single-spi"
233    description: |
234      Describes the mode of SPI bus during the address phase for single/burst
235      write accesses in auto mode. Default value is single mode which should
236      be supported by all memory devices.
237
238  tx-inst-mode:
239    type: string
240    enum:
241      - "single-spi"
242      - "dual-spi"
243      - "quad-spi"
244    default: "single-spi"
245    description: |
246      Describes the mode of SPI bus during the instruction phase for single/burst
247      write accesses in auto mode. The single mode should be supported by all
248      memory devices.
249
250  tx-data-mode:
251    type: string
252    enum:
253      - "single-spi"
254      - "dual-spi"
255      - "quad-spi"
256    default: "single-spi"
257    description: |
258      Describes the mode of SPI bus during the data phase for single/burst
259      write accesses in auto mode. Default value is single mode which should
260      be supported by all memory devices.
261