| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32wb-pll-clock.yaml | 5 STM32WB and STM32WL PLL node.
7 It can be used to describe 2 different PLLs: PLL, PLLSAI1.
8 Only main PLL is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 The PLL output frequency must not exceed:
27 compatible: "st,stm32wb-pll-clock"
42 Main PLL division factor for PLL input clock
49 Main PLL multiplication factor for VCO
55 Main PLL division factor for PLLPCLK
[all …]
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| D | st,stm32g0-pll-clock.yaml | 5 PLL node binding for STM32G0 devices
11 PLL can have up to 3 output clocks and for each output clock, the
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 64 MHz.
22 compatible: "st,stm32g0-pll-clock"
37 Division factor for PLL input clock
44 Main PLL multiplication factor for VCO
50 PLL division factor for PLL P output
56 PLL division factor for PLL Q output
63 PLL division factor for PLLCLK (system clock)
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| D | st,stm32l0-pll-clock.yaml | 5 STM32L0 and STM32L1 Main PLL node binding:
10 The desired PLL frequency can be computed with the following formula:
12 f(PLL) = f(VCO clock) / PLLDIV --> PLLCLK (System Clock)
14 with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
16 The PLL output frequency must not exceed 32 MHz.
18 compatible: "st,stm32l0-pll-clock"
33 PLL output division
43 PLL multiplication factor for VCO
44 The PLL VCO clock frequency must not exceed:
48 If the USB uses the PLL as clock source, the PLL VCO clock must be
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| D | st,stm32f4-pll-clock.yaml | 5 STM32F4 Main PLL node binding:
17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
19 The PLL output frequency must not exceed 80 MHz.
22 compatible: "st,stm32f4-pll-clock"
37 Division factor for the PLL input clock
44 Main PLL multiplication factor for VCO
51 Main PLL division factor for PLLSAI2CLK
61 Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
68 Main PLL (PLL) division factor for I2S and DFSDM
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| D | st,stm32l4-pll-clock.yaml | 5 PLL node binding for STM32L4 and STM32L5 devices
7 It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
8 Only main PLL is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 The PLL output frequency must not exceed 80 MHz.
25 compatible: "st,stm32l4-pll-clock"
40 Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
48 Main PLL multiplication factor for VCO
54 Main PLL division factor for PLLSAI3CLK
[all …]
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| D | st,stm32u0-pll-clock.yaml | 5 STM32U0 Main PLL node binding:
11 PLL can have up to 3 output clocks and for each output clock, the
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 122 MHz.
22 compatible: "st,stm32u0-pll-clock"
37 Division factor M of the PLL
45 PLL frequency multiplication factor N
51 PLL VCO division factor P
57 PLL VCO division factor Q
64 PLL VCO division factor R
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| D | st,stm32f1-pll-clock.yaml | 5 Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
14 The PLL output frequency must not exceed 72 MHz.
17 compatible: "st,stm32f1-pll-clock"
32 Main PLL multiplication factor for VCO
38 Optional HSE divider for PLL entry
43 Optional PLL output divisor to generate a 48MHz USB clock.
44 When set, PLL clock is not divided.
45 Otherwise, PLL output clock is divided by 1.5.
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| D | st,stm32g4-pll-clock.yaml | 5 PLL node binding for STM32G4 devices
11 PLL can have up to 3 output clocks and for each output clock, the
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 170 MHz.
22 compatible: "st,stm32g4-pll-clock"
25 - name: st,stm32l4-pll-clock.yaml
37 Division factor for PLL input clock
44 Main PLL multiplication factor for VCO
50 Main PLL division factor for ADC
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| D | st,stm32f2-pll-clock.yaml | 5 STM32F2 Main PLL node binding:
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
17 The PLL output frequency must not exceed 168 MHz.
20 compatible: "st,stm32f2-pll-clock"
35 Division factor for the PLL input clock
42 PLL multiplication factor for VCO
49 PLL division factor for PLLCLK
59 PLL division factor for PLL48CK
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| D | st,stm32h7-pll-clock.yaml | 5 PLL node binding for STM32H7 devices
7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
14 Each PLL can have up to 3 output clocks and for each output clock, the
23 The PLL output frequency must not exceed 80 MHz.
25 compatible: "st,stm32h7-pll-clock"
48 Main PLL multiplication factor for VCOx
54 PLL division factor for pllx_p_ck
60 PLL division factor for pllx_q_ck
66 PLL division factor for pllx_r_ck
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| D | st,stm32f7-pll-clock.yaml | 5 STM32F7 Main PLL node binding:
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
18 compatible: "st,stm32f7-pll-clock"
33 Division factor for the PLL input clock
40 PLL multiplication factor for VCO
47 PLL division factor for PLLCLK
57 PLL division factor for PLL48CK
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| D | st,stm32h7rs-pll-clock.yaml | 5 PLL node binding for STM32H7RS devices
7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
13 Each PLL can have up to 5 output clocks and for each output clock, the
25 compatible: "st,stm32h7rs-pll-clock"
27 include: st,stm32h7-pll-clock.yaml
33 PLL division factor for pllx_s_ck : valid for PLL1, 2, 3
39 PLL division factor for pllx_t_ck : valid for PLL2
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| D | st,stm32f105-pll-clock.yaml | 5 Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
19 The PLL output frequency must not exceed 72 MHz.
22 compatible: "st,stm32f105-pll-clock"
37 Main PLL multiplication factor for VCO.
58 Optional PLL output divisor to generate a 48MHz USB clock.
59 When set, PLL output clock is not divided.
60 Otherwise, PLL output clock is divided by 1.5.
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| D | nxp,imx-ccm-fnpll.yaml | 5 i.MX CCM Fractional PLL. Output frequency is given by the following
20 Loop divider. Divides PLL feedback loop (effectively multiplying output
27 Numerator of PLL multiplier fraction
33 Denominator of PLL multiplier fraction
38 description: Sets source for PLL input. SOC specific.
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| D | silabs,series2-hfrcodpll.yaml | 5 Can be used as a free-running RC oscillator or with PLL lock to the crystal oscillators HFXO
6 or LFXO. To enable PLL, set the `clocks` property to the source crystal oscillator, and set
9 In PLL mode, `clock-frequency` represents the target PLL frequency.
28 PLL lock mode.
34 description: Automatically re-lock if the PLL loses the lock
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | soc.c | 34 /* PLL Frequency Auto-Calibration Control 0 Register */
44 /* PLL Frequency Auto-Calibration Control 2 Register */
92 * This load operation will ensure PLL setting is taken into in chip_pll_ctrl()
121 * PLL frequency setting = 4 (48MHz)
122 * MCU div = 0 (PLL / 1 = 48 mhz)
123 * FND div = 0 (PLL / 1 = 48 mhz)
124 * USB div = 0 (PLL / 1 = 48 mhz)
125 * UART div = 1 (PLL / 2 = 24 mhz)
126 * SMB div = 1 (PLL / 2 = 24 mhz)
127 * SSPI div = 1 (PLL / 2 = 24 mhz)
[all …]
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_si32_pll.c | 21 LOG_MODULE_REGISTER(pll);
24 SI32_PLL_A_Type *pll; member
67 /* Setup PLL to lock to requested frequency */ in clock_control_si32_pll_on()
68 SI32_PLL_A_initialize(config->pll, 0x00, 0x00, 0x00, 0x000FFF0); in clock_control_si32_pll_on()
69 SI32_PLL_A_set_numerator(config->pll, div_n); in clock_control_si32_pll_on()
70 SI32_PLL_A_set_denominator(config->pll, div_m); in clock_control_si32_pll_on()
72 SI32_PLL_A_select_reference_clock_source_lp0oscdiv(config->pll); in clock_control_si32_pll_on()
75 SI32_PLL_A_select_disable_dco_output(config->pll); in clock_control_si32_pll_on()
76 SI32_PLL_A_set_frequency_adjuster_value(config->pll, 0xFFF); in clock_control_si32_pll_on()
77 SI32_PLL_A_set_output_frequency_range(config->pll, dco_range); in clock_control_si32_pll_on()
[all …]
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| D | clock_stm32f2_f4_f7.c | 22 * @brief Return PLL source
38 * @brief get the pll source frequency
76 /* Get the PLL I2S source : HSE or HSI */ in get_ck48_frequency()
80 /* Get the PLL I2S Q freq. No HAL macro for that */ in get_ck48_frequency()
94 * @brief Set up pll configuration
108 /* There is a Q divider on the PLL to configure the PLL48CK */ in config_pll_sysclock()
118 /* Enable the PLL (PLLON) before setting overdrive. Skipping the PLL in config_pll_sysclock()
120 * (ODSW) but the PLL clock system will be running during the locking in config_pll_sysclock()
136 /* The PLL could still not be locked when returning to the caller in config_pll_sysclock()
137 * function. But the caller doesn't know we've turned on the PLL in config_pll_sysclock()
[all …]
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| /Zephyr-latest/soc/arm/beetle/ |
| D | soc_pll.h | 8 * @file SoC configuration macros for the ARM LTD Beetle SoC PLL.
16 * This header provides the defines to configure the Beetle PLL.
18 * BEETLE PLL main register is the PLLCTRL in the System Control
25 * The formula to calculate the output frequency of the PLL is:
37 * BEETLE PLL has a non bypassable divider by 2 in output
39 * BEETLE PLL derived clock is prescaled [1-16]
42 /* BEETLE PLL Masks */
47 /* BEETLE PLL Configuration */
50 /* BEETLE PLL Supported Frequencies */
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/ |
| D | test_stm32_clock_configuration.c | 40 "Expected sysclk src: PLL (0x%x). Actual: 0x%x", in ZTEST()
71 "Expected PLL src: HSE (%d). Actual PLL src: %d", in ZTEST()
76 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
80 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
85 "Expected PLL src: MSI (%d). Actual PLL src: %d", in ZTEST()
93 /* check RCC_CR_PLLON bit to enable/disable the PLL, but no status function exist */ in ZTEST()
95 /* should not happen : PLL must be disabled when not used */ in ZTEST()
102 "Expected PLL src: none (%d). Actual PLL src: %d", in ZTEST()
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| /Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/ |
| D | stm32h747i_disco_stm32h747xx_m7.overlay | 34 /* DSI HOST dedicated PLL
35 * F_VCO = CLK_IN / pll-idf * 2 * pll-ndiv
36 * PHI = F_VCO / 2 / (1 << pll-odf) = lane_byte_clk
39 pll-ndiv = <100>;
40 pll-idf = <5>;
41 pll-odf = <0>;
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/src/ |
| D | test_stm32_clock_configuration.c | 62 "Expected PLL src: HSE. Actual PLL src: %d", in ZTEST()
66 "Expected PLL src: HSI. Actual PLL src: %d", in ZTEST()
70 "Expected PLL src: CSI. Actual PLL src: %d", in ZTEST()
74 "Expected PLL src: None. Actual PLL src: %d", in ZTEST()
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/ |
| D | test_stm32_clock_configuration.c | 62 "Expected PLL src: HSE. Actual PLL src: %d", in ZTEST()
66 "Expected PLL src: HSI. Actual PLL src: %d", in ZTEST()
70 "Expected PLL src: MSI. Actual PLL src: %d", in ZTEST()
74 "Expected PLL src: None. Actual PLL src: %d", in ZTEST()
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | Kconfig | 24 The main clock is being used to drive the PLL, and thus driving the
35 menu "PLL A"
38 int "PLL MULA"
44 This is the multiplier (MULA) used by the PLL.
49 With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
53 int "PLL DIVA"
57 This is the divider (DIVA) used by the PLL.
63 With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
76 endmenu # PLL A
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/ |
| D | test_stm32_clock_configuration.c | 31 "Expected sysclk src: PLL (0x%x). Actual: 0x%x", in ZTEST()
62 "Expected PLL src: HSE (%d). Actual PLL src: %d", in ZTEST()
66 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
70 "Expected PLL src: CSI (%d). Actual PLL src: %d", in ZTEST()
74 "Expected PLL src: none (%d). Actual PLL src: %d", in ZTEST()
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