Home
last modified time | relevance | path

Searched +full:2 +full:x20 (Results 1 – 25 of 434) sorted by relevance

12345678910>>...18

/Zephyr-latest/dts/arm/atmel/
Dsamd21.dtsi15 tcc-2 = &tcc2;
34 #dma-cells = <2>;
39 reg = <0x42003800 0x20>;
41 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
50 clocks = <&gclk 26>, <&pm 0x20 8>;
62 clocks = <&gclk 26>, <&pm 0x20 9>;
66 channels = <2>;
74 clocks = <&gclk 27>, <&pm 0x20 10>;
78 channels = <2>;
86 clocks = <&gclk 33>, <&pm 0x20 18>;
[all …]
Dsamd20.dtsi12 tc-2 = &tc2;
19 reg = <0x42002000 0x20>;
21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
28 reg = <0x42002800 0x20>;
30 clocks = <&gclk 0x14>, <&pm 0x20 10>;
37 reg = <0x42003800 0x20>;
39 clocks = <&gclk 0x16>, <&pm 0x20 14>;
48 clocks = <&gclk 26>, <&pm 0x20 18>;
54 clocks = <&gclk 0xd>, <&pm 0x20 2>;
60 clocks = <&gclk 0xe>, <&pm 0x20 3>;
[all …]
Dsaml21.dtsi14 tcc-2 = &tcc2;
50 channels = <2>;
76 clocks = <&gclk 20>, <&mclk 0x1c 2>;
94 clocks = <&gclk 24>, <&mclk 0x20 1>;
100 clocks = <&gclk 29>, <&mclk 0x20 2>;
107 clocks = <&gclk 30>, <&mclk 0x20 3>;
Dsamd5x.dtsi25 sercom-2 = &sercom2;
33 tc-2 = &tc2;
39 tcc-2 = &tcc2;
94 #clock-cells = <2>;
127 #dma-cells = <2>;
205 clocks = <&gclk 34>, <&mclk 0x20 0>;
214 clocks = <&gclk 35>, <&mclk 0x20 1>;
223 clocks = <&gclk 36>, <&mclk 0x20 2>;
232 clocks = <&gclk 37>, <&mclk 0x20 3>;
248 #atmel,pin-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/xilinx/
Dzynqmp_rpu.dtsi37 reg = <0xff990200 0x20>,
38 <0xff990220 0x20>,
39 <0xff990040 0x20>,
40 <0xff990060 0x20>;
48 remote-ipi-id = <2>;
49 reg = <0xff990260 0x20>,
50 <0xff990280 0x20>,
51 <0xff990420 0x20>,
52 <0xff990440 0x20>;
66 local-ipi-id = <2>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/
Dra4-cm4-common.dtsi13 reg = <0x400400c0 0x20>;
15 #gpio-cells = <2>;
22 reg = <0x400400e0 0x20>;
24 #gpio-cells = <2>;
31 reg = <0x40040100 0x20>;
33 #gpio-cells = <2>;
40 reg = <0x40040120 0x20>;
42 #gpio-cells = <2>;
49 reg = <0x40070040 0x20>;
Dra-cm4-common.dtsi67 div = <2>;
102 #clock-cells = <2>;
109 #clock-cells = <2>;
116 #clock-cells = <2>;
123 #clock-cells = <2>;
130 #clock-cells = <2>;
137 #clock-cells = <2>;
143 #clock-cells = <2>;
169 reg = <0x40040000 0x20>;
171 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dra2xx.dtsi35 reg = <0x40040000 0x20>;
38 #gpio-cells = <2>;
45 reg = <0x40040020 0x20>;
48 #gpio-cells = <2>;
55 reg = <0x40040040 0x20>;
56 port = <2>;
58 #gpio-cells = <2>;
65 reg = <0x40040060 0x20>;
68 #gpio-cells = <2>;
75 reg = <0x40040080 0x20>;
[all …]
/Zephyr-latest/boards/nxp/frdm_rw612/
DW25Q512JVFIQ_FCB.c19 .deviceModeSeq = {.seqNum = 1, .seqId = 2},
34 0x20),
39 [2] = FC_FLEXSPI_LUT_SEQ(
49 [4 * 2 + 0] =
69 0x20),
77 0x20),
85 0x20),
/Zephyr-latest/tests/net/ppp/driver/src/
Dmain.c50 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
51 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
52 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
66 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
67 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
68 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
73 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
79 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x24, 0x1c, 0x90, 0x7e
89 0x21, 0x7d, 0x22, 0x7d, 0x21, 0x7d, 0x20, 0x7d,
102 0x7d, 0x23, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi53 i2c-smb-2 = &i2c_smb_2;
88 sources = <0 1 2 4 5 10 16 17>;
102 interrupts = <3 2>;
106 #gpio-cells=<2>;
112 interrupts = <2 2>;
116 #gpio-cells=<2>;
123 interrupts = <1 2>;
124 port-id = <2>;
126 #gpio-cells=<2>;
133 interrupts = <0 2>;
[all …]
Dmec172x_common.dtsi42 sources = <0 1 2 3 4 5 6 7
53 sources = <0 1 2 3 4 5 6 7
62 interrupts = <2 0>;
63 girq-id = <2>;
64 sources = <0 1 2 3 4 5 6 7
75 sources = <0 1 2 3 4 5 6 7
86 sources = <0 1 2 3 4 5 6 7
97 sources = <0 1 2 3 4>;
105 sources = <0 1 2 3 4 5 6 7
114 sources = <0 1 2 3 4 5 6 7
[all …]
Dmec5.dtsi56 interrupts = <2 1>;
150 interrupts = <3 2>;
152 #gpio-cells=<2>;
158 interrupts = <2 2>;
160 #gpio-cells=<2>;
167 interrupts = <1 2>;
168 #gpio-cells=<2>;
175 interrupts = <0 2>;
176 #gpio-cells=<2>;
183 interrupts = <4 2>;
[all …]
/Zephyr-latest/boards/nxp/rd_rw612_bga/
DMX25U51245GZ4I00_FCB.c18 .deviceModeSeq = {.seqNum = 1, .seqId = 2},
33 FC_FLEXSPI_4PAD, 0x20),
47 [4 * 2 + 0] = FC_FLEXSPI_LUT_SEQ(
62 FC_FLEXSPI_1PAD, 0x20),
70 0x20),
78 0x20),
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo3_blue.dtsi96 #pwrcfg-cells = <2>;
108 reg = <0x40008000 0x20>;
111 clk-source = <2>;
117 reg = <0x40008020 0x20>;
120 clk-source = <2>;
126 reg = <0x40008040 0x20>;
129 clk-source = <2>;
135 reg = <0x40008060 0x20>;
138 clk-source = <2>;
144 reg = <0x40008080 0x20>;
[all …]
Dambiq_apollo3p_blue.dtsi114 #pwrcfg-cells = <2>;
126 reg = <0x40008000 0x20>;
129 clk-source = <2>;
135 reg = <0x40008020 0x20>;
138 clk-source = <2>;
144 reg = <0x40008040 0x20>;
147 clk-source = <2>;
153 reg = <0x40008060 0x20>;
156 clk-source = <2>;
162 reg = <0x40008080 0x20>;
[all …]
/Zephyr-latest/tests/kconfig/configdefault/
DKconfig30 bool "SYM Y 2"
36 bool "SYM N 2"
219 int "Int 2"
220 default 2
233 default 2
243 default 2
247 default 0x20
250 hex "Hex 0x20"
257 string "Hex 0x20"
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dra4-cm4-common.dtsi48 reg = <0x40040000 0x20>;
51 #gpio-cells = <2>;
58 reg = <0x40040020 0x20>;
61 #gpio-cells = <2>;
68 reg = <0x40040040 0x20>;
69 port = <2>;
71 #gpio-cells = <2>;
78 reg = <0x40040060 0x20>;
81 #gpio-cells = <2>;
88 reg = <0x40040080 0x20>;
[all …]
/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_reg.h18 #define REG_ACCEL_DATA_X0 0x20
92 /* BANK 2 */
148 #define BIT_TEMP_FILT_BW_170 0x20
176 #define SHIFT_INT1_MODE 2
179 #define BIT_TEMP_DIS 0x20
195 #define BIT_DMP_MEM_RESET_EN 0x20
200 #define BIT_COUNT_BIG_ENDIAN 0x20
224 #define BIT_FIFO_WM_TH 0x20
236 #define BIT_INT_PLL_RDY_INT1_EN 0x20
255 #define BIT_TEST_AZ_EN 0x20
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m3ax.dtsi20 reg = <0x40040100 0x20>;
23 #gpio-cells = <2>;
30 reg = <0x40040120 0x20>;
33 #gpio-cells = <2>;
40 reg = <0x40040140 0x20>;
43 #gpio-cells = <2>;
50 reg = <0x40040160 0x20>;
53 #gpio-cells = <2>;
62 reg = <0x400700a0 0x20>;
76 reg = <0x400700c0 0x20>;
[all …]
Dra6-cm4-common.dtsi43 reg = <0x40040000 0x20>;
46 #gpio-cells = <2>;
53 reg = <0x40040020 0x20>;
56 #gpio-cells = <2>;
63 reg = <0x40040040 0x20>;
64 port = <2>;
66 #gpio-cells = <2>;
73 reg = <0x40040060 0x20>;
76 #gpio-cells = <2>;
83 reg = <0x40040080 0x20>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-miwus-int-map.dtsi20 irq-prio = <2>;
25 irq-prio = <2>;
30 irq-prio = <2>;
35 irq-prio = <2>;
36 group-mask = <0x20>;
40 irq-prio = <2>;
45 irq-prio = <2>;
56 irq-prio = <2>;
57 group-mask = <0x20>;
61 irq-prio = <2>;
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-int-map.dtsi20 irq-prio = <2>;
25 irq-prio = <2>;
30 irq-prio = <2>;
35 irq-prio = <2>;
36 group-mask = <0x20>;
40 irq-prio = <2>;
45 irq-prio = <2>;
56 irq-prio = <2>;
61 irq-prio = <2>;
62 group-mask = <0x20>;
[all …]
/Zephyr-latest/tests/drivers/interrupt_controller/intc_plic/src/
Dmain.c19 zassert_equal(1, local_irq_to_reg_index(0x20)); in ZTEST()
21 zassert_equal(2, local_irq_to_reg_index(0x40)); in ZTEST()
28 zassert_equal(4, local_irq_to_reg_offset(0x20)); in ZTEST()
40 zassert_equal(plic_hart_contexts_0[1], 2); in ZTEST()
41 zassert_equal(plic_hart_contexts_0[2], 4); in ZTEST()
51 zassert_equal(plic_hart_contexts_0[2], 3); in ZTEST()
/Zephyr-latest/tests/subsys/modem/modem_ppp/src/
Dmain.c43 0x21, 0x7D, 0x20, 0x7D, 0x24, 0xD1, 0xB5, 0x7E};
48 0x7E, 0xFF, 0x7D, 0x23, 0x7D, 0x20, 0x21, 0x45, 0x7D, 0x20, 0x7D, 0x20, 0x29, 0x87, 0x6E,
49 0x40, 0x7D, 0x20, 0xE8, 0x7D, 0x31, 0xC1, 0xE9, 0x7D, 0x23, 0xFB, 0x7D, 0x25, 0x20, 0x7D,
50 0x2A, 0x2B, 0x36, 0x26, 0x25, 0x7D, 0x32, 0x8C, 0x3E, 0x7D, 0x20, 0x7D, 0x35, 0xBD, 0xF3,
51 0x2D, 0x7D, 0x20, 0x7D, 0x2B, 0x7D, 0x20, 0x7D, 0x27, 0x7D, 0x20, 0x7D, 0x24, 0x7D, 0x20,
52 0x7D, 0x24, 0x7D, 0x2A, 0x7D, 0x20, 0x7D, 0x2A, 0x7D, 0x20, 0xD4, 0x31, 0x7E};
56 0x05, 0x20, 0x0A, 0x2B, 0x36, 0x26, 0x25, 0x12, 0x8C, 0x3E, 0x00, 0x15, 0xBD, 0xF3,
61 0xFB, 0x05, 0x20, 0x0A, 0x2B, 0x36, 0x26, 0x25, 0x12, 0x8C, 0x3E, 0x00, 0x15, 0xBD, 0xF3,
66 0x20, 0x7D, 0x24, 0xD1, 0xB5, 0x7E};
178 unwrapped[unwrapped_pos] = wrapped[wrapped_pos + 1] ^ 0x20; in test_modem_ppp_unwrap()
[all …]

12345678910>>...18