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/Zephyr-latest/samples/subsys/ipc/openamp_rsc_table/boards/
Dcolibri_imx7d_mcimx7d_m4.overlay20 /* use DDR_SYS area as mmio, 0x90000000 0x10000 */
21 reg = <0x90000000 0x10000>;
/Zephyr-latest/dts/arm/nxp/
Dnxp_mcxn94x.dtsi13 ranges = <0x4000000 0x14000000 0x20000000>;
17 ranges = <0x0 0x50000000 0x10000000>;
20 ranges = <0x0 0x10000000 0x4000000>;
25 reg = <0x500c8000 0x1000>, <0x90000000 DT_SIZE_M(8)>;
/Zephyr-latest/boards/st/stm32h745i_disco/
Dstm32h745i_disco_stm32h745xx_m7.dts40 reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
47 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
100 pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
107 pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
114 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
125 pinctrl-0 = <&tim1_ch1_pa8>;
133 pinctrl-0 = <&eth_ref_clk_pa1
151 pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
156 reg = <0x01>;
167 pinctrl-0 = <
[all …]
/Zephyr-latest/boards/st/stm32h750b_dk/
Dstm32h750b_dk.dts29 reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
36 reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */
82 pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_ph9
96 clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>,
105 pixelclk-active = <0>;
106 hsync-active = <0>;
107 vsync-active = <0>;
115 def-back-color-red = <0xFF>;
116 def-back-color-green = <0xFF>;
117 def-back-color-blue = <0xFF>;
[all …]
/Zephyr-latest/boards/st/stm32h747i_disco/
Dstm32h747i_disco_stm32h747xx_m7.dts29 reg = <0xd0000000 DT_SIZE_M(32)>;
36 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
59 #phy-cells = <0>;
124 reg = <0x000ff800 DT_SIZE_K(2)>;
139 pinctrl-0 = <&eth_ref_clk_pa1
151 pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
154 ethernet-phy@0 {
156 reg = <0x00>;
167 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5
189 mode-register = <0x220>;
[all …]
/Zephyr-latest/samples/subsys/fs/littlefs/boards/
Dnucleo_h743zi.overlay11 pinctrl-0 = <&sdmmc1_d0_pc8
35 pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk2_ncs_pc11
45 reg = <0x90000000 DT_SIZE_M(32)>; /* 256 Mbits */
57 storage_partition: partition@0 {
59 reg = <0 DT_SIZE_M(8)>;
/Zephyr-latest/boards/snps/nsim/arc_classic/support/
Dnsim_vpx5.props3 arcver=0x54
10 nsim_isa_big_endian=0
23 nsim_isa_timer_0_int_level=0
25 nsim_isa_timer_1_int_level=0
36 nsim_isa_volatile_limit=0
37 nsim_isa_volatile_disable=0
48 nsim_isa_intvbase_preset=0x0
57 dccm_size=0x40000
58 dccm_base=0x80000000
60 iccm0_size=0x40000
[all …]
Dmdb_vpx5.args17 -Xtimer0_level=0
19 -Xtimer1_level=0
27 -volatile_limit=0
38 -interrupt_base=0x0
47 -dccm_size=0x40000
48 -dccm_base=0x80000000
50 -iccm0_size=0x40000
51 -iccm0_base=0x00000000
79 -Xvec_fast=0
86 -Xvec_mem_topology=0
[all …]
/Zephyr-latest/dts/bindings/flash_controller/
Dst,stm32-qspi-nor.yaml11 reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */
53 - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32)
54 - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38)
68 Indicates the device requires the ULBPR (0x98) command.
/Zephyr-latest/boards/st/stm32f769i_disco/
Dstm32f769i_disco.dts31 reg = <0xc0000000 DT_SIZE_M(16)>;
38 #phy-cells = <0>;
65 gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
85 reg = <0x90000000 DT_SIZE_M(64)>;
118 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
125 pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
132 pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
139 pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pb7>;
146 reg = <0x2a>;
147 int-gpios = <&gpioi 13 0>;
[all …]
/Zephyr-latest/samples/application_development/code_relocation_nocopy/
DREADME.rst20 mapped to 0x10000000.
34 to 0x90000000.
46 to 0x70000000.
60 Address of main function 0x4f9
61 Address of function_in_ext_flash 0x10000001
62 Address of var_ext_sram_data 0x200000a0 (10)
63 Address of function_in_sram 0x20000001
64 Address of var_sram_data 0x200000a4 (10)
/Zephyr-latest/boards/arm/mps3/
Dmps3_common.dtsi26 gpios = <&gpio_led0 0>;
71 gpios = <&gpio_button 0>;
81 null_ptr_detect: null_ptr_detect@0 {
83 /* 0 - CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE> */
84 reg = <0x0 0x400>;
92 reg = <0x60000000 DT_SIZE_M(256)
93 0x70000000 DT_SIZE_M(256)
94 0x80000000 DT_SIZE_M(256)
95 0x90000000 DT_SIZE_M(256)
96 0xa0000000 DT_SIZE_M(256)
[all …]
/Zephyr-latest/boards/mediatek/mt8196/
Dmt8196_adsp.dts15 reg = <0x4e100000 DT_SIZE_K(512)>;
21 reg = <0x90000000 DT_SIZE_M(6)>;
27 reg = <0x90700000 DT_SIZE_M(1)>;
34 core_intc: core_intc@0 {
36 reg = <0 4>;
61 reg = <0x1a014010 4>;
62 status-reg = <0x1a014008>;
63 mask = <0x00007f3f>;
64 interrupts = <1 0 0>;
72 reg = <0x1a014010 4>;
[all …]
/Zephyr-latest/soc/mediatek/mt8xxx/
Dgen_img.py23 FILE_MAGIC = 0xE463BE95
33 # SOCs, but it's always a <=1M region in 0x4xxxxxxx. Just use what we
35 sram_block = 0
40 if addr < 0x40000000 or addr >= 0x50000000:
42 block = addr & ~0xFFFFF
43 assert sram_block in (0, block)
47 assert off < 0x100000
51 # Similar heuristics: current platforms put DRAM either at 0x60000000
52 # or 0x90000000 with no more than 16M of range
54 if (addr >> 28 not in [6, 9]) or (addr & 0x0F000000 != 0):
[all …]
/Zephyr-latest/boards/st/stm32h573i_dk/
Dstm32h573i_dk.dts68 reg = <0x90000000 DT_SIZE_M(64)>;
109 pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
116 pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
123 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
135 pinctrl-0 = <&tim2_ch4_pa3>;
146 pinctrl-0 = <&tim3_ch2_pb5>;
161 pinctrl-0 = <&eth_rxd0_pc4
173 pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
176 ethernet-phy@0 {
178 reg = <0x00>;
[all …]
/Zephyr-latest/boards/st/stm32h7b3i_dk/
Dstm32h7b3i_dk.dts57 reg = <0xd0000000 DT_SIZE_M(16)>;
65 reg = <0x90000000 DT_SIZE_M(64)>;
75 #phy-cells = <0>;
128 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
135 pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_ph14>;
142 pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
149 reg = <0x38>;
150 int-gpios = <&gpioh 2 0>;
155 pinctrl-0 = <&spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15 &spi2_nss_pi0>;
162 pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
[all …]
/Zephyr-latest/boards/st/stm32f723e_disco/
Dstm32f723e_disco.dts45 gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
81 pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
88 pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
95 pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
101 pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_ph5>;
107 pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_ph8>;
113 pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pb4 &spi1_mosi_pb5>;
120 pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb6
128 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
137 pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
/Zephyr-latest/boards/vcc-gnd/yd_stm32h750vb/
Dyd_stm32h750vb.dts95 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
102 pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
111 pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb10
118 reg = <0x90000000 DT_SIZE_M(16)>;
128 storage_partition: partition@0 {
130 reg = <0x0 DT_SIZE_M(16)>;
/Zephyr-latest/boards/alientek/pandora_stm32l475/
Dpandora_stm32l475.dts74 pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
82 reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
119 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
126 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
/Zephyr-latest/boards/st/stm32f412g_disco/
Dstm32f412g_disco.dts27 gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>;
48 gpios = <&gpioa 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
58 gpios = <&gpiog 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
110 pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
117 pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
124 pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb9>;
131 pinctrl-0 = <&spi1_nss_pa15 &spi1_sck_pa5
138 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
144 pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pg6
152 reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
/Zephyr-latest/boards/fanke/fk750m1_vbt6/
Dfk750m1_vbt6.dts43 #size-cells = <0>;
45 st7789v_240x240: st7789v@0 {
48 reg = <0>;
51 x-offset = <0>;
52 y-offset = <0>;
53 vcom = <0x19>;
54 gctrl = <0x35>;
55 vrhs = <0x12>;
56 vdvs = <0x20>;
57 mdac = <0x00>;
[all …]
/Zephyr-latest/boards/st/stm32l496g_disco/
Dstm32l496g_disco.dts106 pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pg10>;
113 pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pd6>;
120 pinctrl-0 = <&lpuart1_tx_pg7 &lpuart1_rx_pg8>;
131 pinctrl-0 = <&tim2_ch1_pa0>;
137 pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb7>;
144 pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pb4 &spi1_mosi_pb5>;
151 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
157 pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
165 pinctrl-0 = < &adc1_in2_pc1>;
173 pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12
[all …]
/Zephyr-latest/dts/arc/synopsys/
Darc_hs4xd.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
84 reg = <0x90000000 0x50000000>;
90 reg = <0xf0005000 0x1000>;
98 reg = <0xf0026000 0x100>;
107 reg = <0xf0027000 0x100>;
116 reg = <0xf0028000 0x100>;
124 reg = <0xf0003000 0x80>;
136 reg = <0xf00014b0 0x4>;
[all …]
Darc_hsdk.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
84 reg = <0x90000000 0x50000000>;
90 reg = <0xf0005000 0x1000>;
98 reg = <0xf0026000 0x1000>;
107 reg = <0xf0027000 0x1000>;
116 reg = <0xf0028000 0x1000>;
124 reg = <0xf0003000 0x1000>;
136 reg = <0xf00014b0 0x4>;
[all …]
/Zephyr-latest/boards/st/stm32h735g_disco/
Dstm32h735g_disco.dts103 pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
110 pinctrl-0 = <&uart7_tx_pf7 &uart7_rx_pf6>;
116 pinctrl-0 = <&i2c4_scl_pf14 &i2c4_sda_pf15>;
125 pinctrl-0 = <&adc1_inp0_pa0_c>;
133 pinctrl-0 = <&eth_rxd0_pc4
146 pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
149 ethernet-phy@0 {
151 reg = <0x00>;
157 pinctrl-0 = <&sdmmc1_d0_pc8
168 pinctrl-0 = <&octospim_p1_clk_pf10 &octospim_p1_ncs_pg6
[all …]

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