Lines Matching +full:0 +full:x90000000
29 reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
36 reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */
82 pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_ph9
96 clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>,
105 pixelclk-active = <0>;
106 hsync-active = <0>;
107 vsync-active = <0>;
115 def-back-color-red = <0xFF>;
116 def-back-color-green = <0xFF>;
117 def-back-color-blue = <0xFF>;
152 pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
160 pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6
170 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
181 partition@0 {
182 reg = <0x0 DT_SIZE_M(64)>;
189 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
196 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
214 mode-register = <0x230>;
215 refresh-rate = <0x603>;
232 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
251 pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;