1/*
2 * Copyright (c) 2021 SILA Embedded Solutions GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h735Xg.dtsi>
9#include <st/h7/stm32h735igkx-pinctrl.dtsi>
10#include "pmod_connector.dtsi"
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12
13/ {
14	model = "STMicroelectronics STM32H735G DISCOVERY board";
15	compatible = "st,stm32h735g-disco";
16
17	chosen {
18		zephyr,console = &usart3;
19		zephyr,shell-uart = &usart3;
20		zephyr,sram = &sram0;
21		zephyr,flash = &flash0;
22		zephyr,canbus = &fdcan1;
23	};
24
25	leds {
26		compatible = "gpio-leds";
27		red_led: led_1 {
28			gpios = <&gpioc 2 GPIO_ACTIVE_LOW>;
29			label = "User LD2";
30		};
31		green_led: led_2 {
32			gpios = <&gpioc 3 GPIO_ACTIVE_LOW>;
33			label = "User LD1";
34		};
35	};
36
37	gpio_keys {
38		compatible = "gpio-keys";
39		user_button: button {
40			label = "User";
41			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
42			zephyr,code = <INPUT_KEY_0>;
43		};
44	};
45
46	aliases {
47		led0 = &red_led;
48		led1 = &green_led;
49		sw0 = &user_button;
50		volt-sensor1 = &vbat;
51	};
52};
53
54&clk_hse {
55	clock-frequency = <DT_FREQ_M(25)>;
56	status = "okay";
57};
58
59&clk_lse {
60	status = "okay";
61};
62
63&clk_lsi {
64	status = "okay";
65};
66
67&clk_hsi48 {
68	status = "okay";
69};
70
71&pll {
72	div-m = <5>;
73	mul-n = <110>;
74	div-p = <1>;
75	div-q = <4>;
76	div-r = <2>;
77	clocks = <&clk_hse>;
78	status = "okay";
79};
80
81&pll2 {
82	div-m = <5>;
83	mul-n = <80>;
84	div-p = <5>;
85	div-q = <5>;
86	div-r = <5>;
87	clocks = <&clk_hse>;
88	status = "okay";
89};
90
91&rcc {
92	clocks = <&pll>;
93	clock-frequency = <DT_FREQ_M(550)>;
94	d1cpre = <1>;
95	hpre = <2>;
96	d1ppre = <2>;
97	d2ppre1 = <2>;
98	d2ppre2 = <2>;
99	d3ppre = <2>;
100};
101
102&usart3 {
103	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
104	pinctrl-names = "default";
105	current-speed = <115200>;
106	status = "okay";
107};
108
109&uart7 {
110	pinctrl-0 = <&uart7_tx_pf7 &uart7_rx_pf6>;
111	pinctrl-names = "default";
112	current-speed = <115200>;
113};
114
115&i2c4 {
116	pinctrl-0 = <&i2c4_scl_pf14 &i2c4_sda_pf15>;
117	pinctrl-names = "default";
118};
119
120&rng {
121	status = "okay";
122};
123
124&adc1 {
125	pinctrl-0 = <&adc1_inp0_pa0_c>;
126	pinctrl-names = "default";
127	st,adc-clock-source = "SYNC";
128	st,adc-prescaler = <4>;
129	status = "okay";
130};
131
132&mac {
133	pinctrl-0 = <&eth_rxd0_pc4
134		     &eth_rxd1_pc5
135		     &eth_ref_clk_pa1
136		     &eth_crs_dv_pa7
137		     &eth_tx_en_pb11
138		     &eth_txd0_pb12
139		     &eth_txd1_pb13>;
140	pinctrl-names = "default";
141	status = "okay";
142};
143
144&mdio {
145	status = "okay";
146	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
147	pinctrl-names = "default";
148
149	ethernet-phy@0 {
150		compatible = "ethernet-phy";
151		reg = <0x00>;
152		status = "okay";
153	};
154};
155
156&sdmmc1 {
157	pinctrl-0 = <&sdmmc1_d0_pc8
158		     &sdmmc1_d1_pc9
159		     &sdmmc1_d2_pc10
160		     &sdmmc1_d3_pc11
161		     &sdmmc1_ck_pc12
162		     &sdmmc1_cmd_pd2>;
163	pinctrl-names = "default";
164	cd-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>;
165};
166
167&octospi1 {
168	pinctrl-0 = <&octospim_p1_clk_pf10 &octospim_p1_ncs_pg6
169		     &octospim_p1_io0_pd11 &octospim_p1_io1_pd12
170		     &octospim_p1_io2_pe2 &octospim_p1_io3_pd13
171		     &octospim_p1_io4_pd4 &octospim_p1_io5_pd5
172		     &octospim_p1_io6_pg9 &octospim_p1_io7_pd7
173		     &octospim_p1_dqs_pb2>;
174	pinctrl-names = "default";
175
176	status = "okay";
177
178	mx25lm51245: ospi-nor-flash@90000000 {
179		compatible = "st,stm32-ospi-nor";
180		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
181		ospi-max-frequency = <DT_FREQ_M(50)>;
182		spi-bus-width = <OSPI_OPI_MODE>;
183		data-rate = <OSPI_DTR_TRANSFER>;
184		status = "okay";
185
186		partitions {
187			   compatible = "fixed-partitions";
188			   #address-cells = <1>;
189			   #size-cells = <1>;
190
191			   partition@0 {
192			       label = "nor";
193			       reg = <0x00000000 DT_SIZE_M(4)>;
194			   };
195		};
196	};
197};
198
199&rtc {
200	clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
201		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
202	status = "okay";
203
204	backup_regs {
205		status = "okay";
206	};
207};
208
209&fdcan1 {
210	pinctrl-0 = <&fdcan1_rx_ph14 &fdcan1_tx_ph13>;
211	pinctrl-names = "default";
212	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
213		 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
214	status = "okay";
215
216	can-transceiver {
217		max-bitrate = <8000000>;
218	};
219};
220
221&fdcan2 {
222	pinctrl-0 = <&fdcan2_rx_pb5 &fdcan2_tx_pb6>;
223	pinctrl-names = "default";
224	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
225		 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
226	status = "okay";
227
228	can-transceiver {
229		max-bitrate = <8000000>;
230	};
231};
232
233&fdcan3 {
234	pinctrl-0 = <&fdcan3_rx_pf6 &fdcan3_tx_pf7>;
235	pinctrl-names = "default";
236	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
237		 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
238	/* Solder bridges SB29 and SB30 need to be closed for this to work */
239	status = "disabled";
240
241	can-transceiver {
242		max-bitrate = <8000000>;
243	};
244};
245
246zephyr_udc0: &usbotg_hs {
247	status = "okay";
248	pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
249	pinctrl-names = "default";
250};
251