1/*
2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h7b3Xi.dtsi>
9#include <st/h7/stm32h7b3lihxq-pinctrl.dtsi>
10#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11#include "arduino_r3_connector.dtsi"
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	model = "STMicroelectronics STM32H7B3I DISCOVERY KIT board";
16	compatible = "st,stm32h7b3i-dk";
17
18	chosen {
19		zephyr,console = &usart1;
20		zephyr,shell-uart = &usart1;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23		zephyr,display = &ltdc;
24		zephyr,canbus = &fdcan1;
25		zephyr,touch = &ft5336;
26	};
27
28	leds {
29		compatible = "gpio-leds";
30		red_led: led_0 {
31			gpios = <&gpiog 11 GPIO_ACTIVE_HIGH>;
32			label = "User LD1";
33		};
34		blue_led: led_1 {
35			gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
36			label = "User LD2";
37		};
38	};
39
40	gpio_keys {
41		compatible = "gpio-keys";
42		user_button: button {
43			label = "User PB";
44			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
45			zephyr,code = <INPUT_KEY_0>;
46		};
47	};
48
49	lvgl_pointer {
50		compatible = "zephyr,lvgl-pointer-input";
51		input = <&ft5336>;
52	};
53
54	sdram2: sdram@d0000000 {
55		compatible = "zephyr,memory-region", "mmio-sram";
56		device_type = "memory";
57		reg = <0xd0000000 DT_SIZE_M(16)>;
58		zephyr,memory-region = "SDRAM2";
59		/* Frame buffer memory cache will cause screen flickering. */
60		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
61	};
62
63	octo_nor: memory@90000000 {
64		compatible = "zephyr,memory-region";
65		reg = <0x90000000 DT_SIZE_M(64)>;
66		zephyr,memory-region = "EXTMEM";
67		/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
68		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
69	};
70
71	transceiver0: can-phy0 {
72		compatible = "microchip,mcp2562fd", "can-transceiver-gpio";
73		standby-gpios = <&gpioh 8 GPIO_ACTIVE_HIGH>;
74		max-bitrate = <5000000>;
75		#phy-cells = <0>;
76	};
77
78	aliases {
79		led0 = &blue_led;
80		led1 = &red_led;
81		sw0 = &user_button;
82	};
83};
84
85&clk_hsi48 {
86	status = "okay";
87};
88
89&clk_hse {
90	clock-frequency = <DT_FREQ_M(24)>;
91	status = "okay";
92};
93
94/* PLL1P is used for system clock (280 MHz), PLL1Q is used for FDCAN bit quantum clock (80 MHz) */
95&pll {
96	div-m = <12>;
97	mul-n = <280>;
98	div-p = <2>;
99	div-q = <7>;
100	div-r = <2>;
101	clocks = <&clk_hse>;
102	status = "okay";
103};
104
105/* PLL3R is used for outputting 9 MHz pixel clock for LTDC */
106&pll3 {
107	div-m = <8>;
108	mul-n = <60>;
109	div-p = <2>;
110	div-q = <2>;
111	div-r = <20>;
112	clocks = <&clk_hse>;
113	status = "okay";
114};
115
116&rcc {
117	clocks = <&pll>;
118	clock-frequency = <DT_FREQ_M(280)>;
119	d1cpre = <1>;
120	hpre = <1>;
121	d1ppre = <2>;
122	d2ppre1 = <2>;
123	d2ppre2 = <2>;
124	d3ppre = <2>;
125};
126
127&usart1 {
128	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
129	pinctrl-names = "default";
130	current-speed = <115200>;
131	status = "okay";
132};
133
134&uart4 {
135	pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_ph14>;
136	pinctrl-names = "default";
137	current-speed = <115200>;
138	status = "okay";
139};
140
141&i2c4 {
142	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
143	pinctrl-names = "default";
144	clock-frequency = <I2C_BITRATE_FAST>;
145	status = "okay";
146
147	ft5336: ft5336@38 {
148		compatible = "focaltech,ft5336";
149		reg = <0x38>;
150		int-gpios = <&gpioh 2 0>;
151	};
152};
153
154&spi2 {
155	pinctrl-0 = <&spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15 &spi2_nss_pi0>;
156	pinctrl-names = "default";
157	status = "okay";
158};
159
160/* Connect solder bridges SB3, SB4 and SB5 to use CAN connector (CN21) */
161&fdcan1 {
162	pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
163	pinctrl-names = "default";
164	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
165		 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
166	phys = <&transceiver0>;
167	status = "okay";
168};
169
170&fmc {
171	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
172		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
173		     &fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
174		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
175		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
176		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
177		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
178		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
179		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
180		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
181		     &fmc_d15_pd10>;
182	pinctrl-names = "default";
183	status = "okay";
184
185	sdram {
186		status = "okay";
187		power-up-delay = <100>;
188		num-auto-refresh = <8>;
189		mode-register = <0x220>;
190		refresh-rate = <0x603>;
191		bank@1 {
192			reg = <1>;
193			st,sdram-control = <STM32_FMC_SDRAM_NC_9
194						STM32_FMC_SDRAM_NR_12
195						STM32_FMC_SDRAM_MWID_16
196						STM32_FMC_SDRAM_NB_4
197						STM32_FMC_SDRAM_CAS_2
198						STM32_FMC_SDRAM_SDCLK_PERIOD_3
199						STM32_FMC_SDRAM_RBURST_ENABLE
200						STM32_FMC_SDRAM_RPIPE_2>;
201			st,sdram-timing = <2 7 4 7 2 2 2>;
202		};
203	};
204};
205
206&sdmmc1 {
207	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
208		     &sdmmc1_d2_pc10 &sdmmc1_d3_pc11
209		     &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
210	pinctrl-names = "default";
211	cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
212	status = "okay";
213};
214
215&ltdc {
216	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
217		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
218		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
219		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
220		     &ltdc_b0_pj12 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
221		     &ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
222		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi12 &ltdc_vsync_pi13>;
223	pinctrl-names = "default";
224	disp-on-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
225	bl-ctrl-gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>;
226	ext-sdram = <&sdram2>;
227	status = "okay";
228
229	width = <480>;
230	height = <272>;
231	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
232	display-timings {
233		compatible = "zephyr,panel-timing";
234		de-active = <0>;
235		pixelclk-active = <0>;
236		hsync-active = <0>;
237		vsync-active = <0>;
238		hsync-len = <1>;
239		vsync-len = <10>;
240		hback-porch = <43>;
241		vback-porch = <12>;
242		hfront-porch = <8>;
243		vfront-porch = <4>;
244	};
245	def-back-color-red = <0xFF>;
246	def-back-color-green = <0xFF>;
247	def-back-color-blue = <0xFF>;
248};
249
250&octospi1 {
251	pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pg6
252		     &octospim_p1_io0_pd11 &octospim_p1_io1_pf9
253		     &octospim_p1_io2_pf7 &octospim_p1_io3_pf6
254		     &octospim_p1_io4_pc1 &octospim_p1_io5_ph3
255		     &octospim_p1_io6_pg9 &octospim_p1_io7_pd7
256		     &octospim_p1_dqs_pc5>;
257	pinctrl-names = "default";
258
259	status = "okay";
260
261	mx25lm51245: ospi-nor-flash@90000000 {
262		compatible = "st,stm32-ospi-nor";
263		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
264		ospi-max-frequency = <DT_FREQ_M(50)>;
265		spi-bus-width = <OSPI_OPI_MODE>;
266		data-rate = <OSPI_DTR_TRANSFER>;
267		status = "okay";
268
269		partitions {
270			   compatible = "fixed-partitions";
271			   #address-cells = <1>;
272			   #size-cells = <1>;
273
274			   partition@0 {
275			       label = "nor";
276			       reg = <0x00000000 DT_SIZE_M(4)>;
277			   };
278		};
279	};
280};
281