1/*
2 * Copyright (c) 2018 Yong Jin
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/f7/stm32f769Xi.dtsi>
9#include <st/f7/stm32f769nihx-pinctrl.dtsi>
10#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11#include "arduino_r3_connector.dtsi"
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	model = "STMicroelectronics STM32F769I DISCOVERY board";
16	compatible = "st,stm32f769I-disco";
17
18	chosen {
19		zephyr,console = &usart1;
20		zephyr,shell-uart = &usart1;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23		zephyr,dtcm = &dtcm;
24		zephyr,flash-controller = &mx25l51245g;
25		zephyr,touch = &ft6202;
26	};
27
28	sdram1: sdram@c0000000 {
29		compatible = "zephyr,memory-region", "mmio-sram";
30		device_type = "memory";
31		reg = <0xc0000000 DT_SIZE_M(16)>;
32		zephyr,memory-region = "SDRAM1";
33		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
34	};
35
36	otghs_ulpi_phy: otghs_ulpis_phy {
37		compatible = "usb-ulpi-phy";
38		#phy-cells = <0>;
39	};
40
41	leds {
42		compatible = "gpio-leds";
43		red_led_1:led_1 {
44			gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
45			label = "User LD1";
46		};
47		green_led_2:led_2 {
48			gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
49			label = "User LD2";
50		};
51		green_led_3:led_3 {
52			gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>;
53			label = "User LD3";
54		};
55		red_led_4:led_4 {
56			gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>;
57			label = "User LD4";
58		};
59	};
60
61	gpio_keys {
62		compatible = "gpio-keys";
63		user_button: button {
64			label = "User";
65			gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
66			zephyr,code = <INPUT_KEY_0>;
67		};
68	};
69
70	lvgl_pointer {
71		compatible = "zephyr,lvgl-pointer-input";
72		input = <&ft6202>;
73	};
74
75	aliases {
76		led0 = &red_led_1;
77		led1 = &green_led_2;
78		led2 = &green_led_3;
79		led3 = &red_led_4;
80		sw0 = &user_button;
81	};
82
83	quadspi_memory_avail: memory-avail@90000000 {
84		compatible = "zephyr,memory-region", "mmio-sram";
85		reg = <0x90000000 DT_SIZE_M(64)>;
86		zephyr,memory-region = "QSPI_AVAIL";
87		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
88	};
89};
90
91&clk_hse {
92	clock-frequency = <DT_FREQ_M(25)>;
93	status = "okay";
94};
95
96&pll {
97	div-m = <25>;
98	mul-n = <432>;
99	div-p = <2>;
100	div-q = <9>;
101	clocks = <&clk_hse>;
102	status = "okay";
103};
104
105&rcc {
106	clocks = <&pll>;
107	clock-frequency = <DT_FREQ_M(216)>;
108	ahb-prescaler = <1>;
109	apb1-prescaler = <4>;
110	apb2-prescaler = <2>;
111};
112
113arduino_i2c: &i2c1 {};
114arduino_spi: &spi2 {};
115arduino_serial: &usart6 {};
116
117&usart1 {
118	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
119	pinctrl-names = "default";
120	current-speed = <115200>;
121	status = "okay";
122};
123
124&usart6 {
125	pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
126	pinctrl-names = "default";
127	current-speed = <115200>;
128	status = "okay";
129};
130
131&i2c1 {
132	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
133	pinctrl-names = "default";
134	status = "okay";
135	clock-frequency = <I2C_BITRATE_FAST>;
136};
137
138&i2c4 {
139	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pb7>;
140	pinctrl-names = "default";
141	status = "okay";
142	clock-frequency = <I2C_BITRATE_FAST>;
143
144	ft6202: ft6202@2a {
145		compatible = "focaltech,ft5336";
146		reg = <0x2a>;
147		int-gpios = <&gpioi 13 0>;
148	};
149};
150
151&spi2 {
152	pinctrl-0 = <&spi2_nss_pa11 &spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15>;
153	pinctrl-names = "default";
154	status = "okay";
155};
156
157&mac {
158	status = "okay";
159	pinctrl-0 = <&eth_mdc_pc1
160		     &eth_rxd0_pc4
161		     &eth_rxd1_pc5
162		     &eth_ref_clk_pa1
163		     &eth_mdio_pa2
164		     &eth_crs_dv_pa7
165		     &eth_tx_en_pg11
166		     &eth_txd0_pg13
167		     &eth_txd1_pg14>;
168	pinctrl-names = "default";
169};
170
171&sdmmc2 {
172	status = "okay";
173	pinctrl-0 = <&sdmmc2_d0_pg9 &sdmmc2_d1_pg10
174		     &sdmmc2_d2_pb3 &sdmmc2_d3_pb4
175		     &sdmmc2_ck_pd6 &sdmmc2_cmd_pd7>;
176	pinctrl-names = "default";
177	cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
178};
179
180&quadspi {
181	pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb6
182		     &quadspi_bk1_io0_pc9 &quadspi_bk1_io1_pc10
183		     &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>;
184	pinctrl-names = "default";
185	status = "okay";
186
187	mx25l51245g: qspi-nor-flash@90000000 {
188		compatible = "st,stm32-qspi-nor";
189		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
190		qspi-max-frequency = <DT_FREQ_M(66)>;
191		status = "okay";
192
193		partitions {
194			compatible = "fixed-partitions";
195			#address-cells = <1>;
196			#size-cells = <1>;
197
198			slot1_partition: partition@0 {
199				label = "image-1";
200				reg = <0x00000000 DT_SIZE_K(16)>;
201				};
202
203			storage_partition: partition@1a0000 {
204				label = "storage";
205				reg = <0x001a0000 DT_SIZE_M(62)>;
206			};
207		};
208	};
209};
210
211&fmc {
212	status = "okay";
213	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5
214		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_ph2 &fmc_sdne0_ph3
215		     &fmc_sdnras_pf11 &fmc_sdncas_pg15
216		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3
217		     &fmc_a4_pf4 &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13
218		     &fmc_a8_pf14 &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
219		     &fmc_a12_pg2 &fmc_a14_pg4 &fmc_a15_pg5
220		     &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1
221		     &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10
222		     &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14
223		     &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10
224		     &fmc_d16_ph8 &fmc_d17_ph9 &fmc_d18_ph10 &fmc_d19_ph11
225		     &fmc_d20_ph12 &fmc_d21_ph13 &fmc_d22_ph14 &fmc_d23_ph15
226		     &fmc_d24_pi0 &fmc_d25_pi1 &fmc_d26_pi2 &fmc_d27_pi3
227		     &fmc_d28_pi6 &fmc_d29_pi7 &fmc_d30_pi9 &fmc_d31_pi10>;
228	pinctrl-names = "default";
229
230	sdram {
231		status = "okay";
232
233		power-up-delay = <100>;
234		num-auto-refresh = <8>;
235		mode-register = <0x230>;
236		refresh-rate = <603>;
237
238		bank@0 {
239			reg = <0>;
240
241			st,sdram-control = <STM32_FMC_SDRAM_NC_8
242					    STM32_FMC_SDRAM_NR_12
243					    STM32_FMC_SDRAM_MWID_32
244					    STM32_FMC_SDRAM_NB_4
245					    STM32_FMC_SDRAM_CAS_3
246					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
247					    STM32_FMC_SDRAM_RBURST_ENABLE
248					    STM32_FMC_SDRAM_RPIPE_0>;
249			st,sdram-timing = <2 6 4 6 2 2 2>;
250		};
251	};
252};
253
254zephyr_udc0: &usbotg_hs {
255	pinctrl-0 = <&usb_otg_hs_ulpi_ck_pa5
256			&usb_otg_hs_ulpi_d0_pa3
257			&usb_otg_hs_ulpi_d1_pb0
258			&usb_otg_hs_ulpi_d2_pb1
259			&usb_otg_hs_ulpi_d3_pb10
260			&usb_otg_hs_ulpi_d4_pb11
261			&usb_otg_hs_ulpi_d5_pb12
262			&usb_otg_hs_ulpi_d6_pb13
263			&usb_otg_hs_ulpi_d7_pb5
264			&usb_otg_hs_ulpi_stp_pc0
265			&usb_otg_hs_ulpi_dir_pi11
266			&usb_otg_hs_ulpi_nxt_ph4>;
267	pinctrl-names = "default";
268	maximum-speed = "high-speed";
269	phys = <&otghs_ulpi_phy>;
270	status = "okay";
271};
272