1/*
2 * Copyright (c) 2019 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h747Xi_m7.dtsi>
9#include <st/h7/stm32h747xihx-pinctrl.dtsi>
10#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11#include "stm32h747i_disco.dtsi"
12
13/ {
14	model = "STMicroelectronics STM32H747I DISCOVERY board";
15	compatible = "st,stm32h747i-disco";
16
17	/* HW resources are split between CM7 and CM4 */
18	chosen {
19		zephyr,console = &usart1;
20		zephyr,shell-uart = &usart1;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23		zephyr,flash-controller = &mt25ql512ab1;
24	};
25
26	sdram2: sdram@d0000000 {
27		compatible = "zephyr,memory-region", "mmio-sram";
28		device_type = "memory";
29		reg = <0xd0000000 DT_SIZE_M(32)>;
30		zephyr,memory-region = "SDRAM2";
31		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
32	};
33
34	ext_memory: memory@90000000 {
35		compatible = "zephyr,memory-region";
36		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
37		zephyr,memory-region = "EXTMEM";
38		/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
39		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
40	};
41
42	leds {
43		green_led_1:led_1 {
44			status = "okay";
45		};
46		orange_led_2:led_2 {
47			status = "okay";
48		};
49	};
50
51	gpio_keys {
52		wake_up: button {
53			status = "okay";
54		};
55	};
56
57	otghs_ulpi_phy: otghs_ulpis_phy {
58		compatible = "usb-ulpi-phy";
59		#phy-cells = <0>;
60	};
61
62	aliases {
63		led0 = &green_led_1;
64		led1 = &orange_led_2;
65		sw0 = &wake_up;
66	};
67};
68
69&clk_hse {
70	clock-frequency = <DT_FREQ_M(25)>;
71	status = "okay";
72};
73
74&clk_hsi48 {
75	status = "okay";
76};
77
78&pll {
79	div-m = <5>;
80	mul-n = <160>;
81	div-p = <2>;
82	div-q = <4>;
83	div-r = <2>;
84	clocks = <&clk_hse>;
85	status = "okay";
86};
87
88&pll2 {
89	div-m = <5>;
90	mul-n = <96>;
91	div-p = <2>;
92	div-q = <4>;
93	div-r = <10>;
94	clocks = <&clk_hse>;  /* Assuming 25MHz HSE */
95	status = "okay";
96};
97
98&rcc {
99	clocks = <&pll>;
100	clock-frequency = <DT_FREQ_M(400)>;
101};
102
103&usart1 {
104	status = "okay";
105};
106
107&uart8 {
108	/* status = "okay"; */
109};
110
111&spi5 {
112	status = "okay";
113};
114
115&flash0 {
116	partitions {
117		compatible = "fixed-partitions";
118		#address-cells = <1>;
119		#size-cells = <1>;
120
121		/* Set 2KB of storage at the end of first 1MB flash */
122		storage_partition: partition@ff800 {
123			label = "storage";
124			reg = <0x000ff800 DT_SIZE_K(2)>;
125		};
126	};
127};
128
129&mac {
130	/*
131	 * From UM2411 Rev 4:
132	 * With the default setting, the Ethernet feature is not working due
133	 * of a pin conflict between ETH_MDC and SAI4_D1 of the MEMs digital
134	 * microphone.
135	 * Cf Ethernet section in board documentation for more information on
136	 * the hw modification to be done to enable it.
137	 */
138	status = "okay";
139	pinctrl-0 = <&eth_ref_clk_pa1
140		     &eth_crs_dv_pa7
141		     &eth_rxd0_pc4
142		     &eth_rxd1_pc5
143		     &eth_tx_en_pg11
144		     &eth_txd0_pg13
145		     &eth_txd1_pg12>;
146	pinctrl-names = "default";
147};
148
149&mdio {
150	status = "okay";
151	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
152	pinctrl-names = "default";
153
154	ethernet-phy@0 {
155		compatible = "ethernet-phy";
156		reg = <0x00>;
157		status = "okay";
158	};
159};
160
161&rng {
162	status = "okay";
163};
164
165&fmc {
166	status = "okay";
167	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5
168		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
169		     &fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
170		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
171		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
172		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
173		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
174		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
175		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
176		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
177		     &fmc_d15_pd10 &fmc_d16_ph8 &fmc_d17_ph9 &fmc_d18_ph10
178		     &fmc_d19_ph11 &fmc_d20_ph12 &fmc_d21_ph13 &fmc_d22_ph14
179		     &fmc_d23_ph15 &fmc_d24_pi0 &fmc_d25_pi1 &fmc_d26_pi2
180		     &fmc_d27_pi3 &fmc_d28_pi6 &fmc_d29_pi7 &fmc_d30_pi9
181		     &fmc_d31_pi10>;
182	pinctrl-names = "default";
183
184	sdram {
185		status = "okay";
186
187		power-up-delay = <100>;
188		num-auto-refresh = <8>;
189		mode-register = <0x220>;
190		refresh-rate = <603>;
191
192		bank@1 {
193			reg = <1>;
194
195			st,sdram-control = <STM32_FMC_SDRAM_NC_9
196					    STM32_FMC_SDRAM_NR_12
197					    STM32_FMC_SDRAM_MWID_32
198					    STM32_FMC_SDRAM_NB_4
199					    STM32_FMC_SDRAM_CAS_2
200					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
201					    STM32_FMC_SDRAM_RBURST_ENABLE
202					    STM32_FMC_SDRAM_RPIPE_0>;
203			st,sdram-timing = <2 6 4 6 2 2 2>;
204		};
205	};
206};
207
208zephyr_udc0: &usbotg_hs {
209	pinctrl-0 = <&usb_otg_hs_ulpi_ck_pa5
210			&usb_otg_hs_ulpi_d0_pa3
211			&usb_otg_hs_ulpi_d1_pb0
212			&usb_otg_hs_ulpi_d2_pb1
213			&usb_otg_hs_ulpi_d3_pb10
214			&usb_otg_hs_ulpi_d4_pb11
215			&usb_otg_hs_ulpi_d5_pb12
216			&usb_otg_hs_ulpi_d6_pb13
217			&usb_otg_hs_ulpi_d7_pb5
218			&usb_otg_hs_ulpi_stp_pc0
219			&usb_otg_hs_ulpi_dir_pi11
220			&usb_otg_hs_ulpi_nxt_ph4>;
221	pinctrl-names = "default";
222	maximum-speed = "high-speed";
223	/* Include the USB1ULPIEN clock enable bit */
224	clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x06000000>,
225		 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
226	phys = <&otghs_ulpi_phy>;
227	status = "okay";
228};
229
230&sdmmc1 {
231	status = "okay";
232	clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>,
233			<&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;
234	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
235			&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
236			&sdmmc1_d4_pb8 &sdmmc1_d5_pb9
237			&sdmmc1_d6_pc6 &sdmmc1_d7_pc7
238			&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
239	pinctrl-names = "default";
240	cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
241};
242
243&quadspi {
244	pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pg6
245		     &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pf9
246		     &quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6
247		     &quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3
248		     &quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>;
249	pinctrl-names = "default";
250	dual-flash;
251	status = "okay";
252
253	mt25ql512ab1: qspi-nor-flash-1@90000000 {
254		compatible = "st,stm32-qspi-nor";
255		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
256		qspi-max-frequency = <72000000>;
257		spi-bus-width = <4>;
258		reset-cmd;
259		status = "okay";
260
261		partitions {
262			   compatible = "fixed-partitions";
263			   #address-cells = <1>;
264			   #size-cells = <1>;
265
266			   partition@0 {
267			       reg = <0x0 DT_SIZE_M(64)>;
268			   };
269		};
270	};
271
272	mt25ql512ab2: qspi-nor-flash-2@90000000 {
273		compatible = "st,stm32-qspi-nor";
274		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
275		qspi-max-frequency = <72000000>;
276		status = "okay";
277	};
278};
279
280arduino_spi: &spi5 {};
281
282/* alias used by display shields with touch control */
283qsh_030_i2c: &i2c4 {
284	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
285	pinctrl-names = "default";
286	clock-frequency = <I2C_BITRATE_FAST>;
287	status = "okay";
288};
289
290/* alias used by display shields */
291zephyr_mipi_dsi: &mipi_dsi {};
292
293/* alias used by LCD display shields */
294zephyr_lcd_controller: &ltdc {};
295