1/* Copyright 2024 The ChromiumOS Authors
2 * SPDX-License-Identifier: Apache-2.0
3 */
4#include <mem.h>
5
6/dts-v1/;
7/ {
8
9	#address-cells = <1>;
10	#size-cells = <1>;
11
12	sram0: memory@4e100000 {
13		 device_type = "memory";
14		 compatible = "mmio-sram";
15		 reg = <0x4e100000 DT_SIZE_K(512)>;
16	};
17
18	dram0: memory@90000000 {
19		device_type = "memory";
20		compatible = "mmio-sram";
21		reg = <0x90000000 DT_SIZE_M(6)>;
22	};
23
24	dram1: memory@90700000 {
25		device_type = "memory";
26		compatible = "mmio-sram";
27		reg = <0x90700000 DT_SIZE_M(1)>;
28	};
29
30	soc {
31		#address-cells = <1>;
32		#size-cells = <1>;
33
34		core_intc: core_intc@0 {
35			compatible = "cdns,xtensa-core-intc";
36			reg = <0 4>;
37			interrupt-controller;
38			#interrupt-cells = <3>;
39		};
40
41		/* The 8196 interrupt controller is actually more complicated
42		 * than the driver here supports.  There are 64 total
43		 * interrupt inputs, each of which is a associated with one of
44		 * 16 "groups", each of which is wired to a separate Xtensa
45		 * architectural interrupt. (Whether the mapping of external
46		 * interrupts to groups is mutable is an open question, the
47		 * values here appear to be hardware defaults).  We represent
48		 * each group (strictly each of the high and low 32 interrupts
49		 * of each group) as a separate adsp_intc controller, pointing
50		 * at the same status and enable registers, but with disjoint
51		 * masks.  Note that this disallows configurations where a
52		 * single controller needs to manage interrupts in both the
53		 * high and low 32 bits of the set, but no current drivers
54		 * rely on such a configuration.
55		 */
56
57		intc_g1: intc_g1@1a014010 {
58			compatible = "mediatek,adsp_intc";
59			interrupt-controller;
60			#interrupt-cells = <3>;
61			reg = <0x1a014010 4>;
62			status-reg = <0x1a014008>;
63			mask = <0x00007f3f>;
64			interrupts = <1 0 0>;
65			interrupt-parent = <&core_intc>;
66		};
67
68		intc_g2: intc_g2@1a014010 {
69			compatible = "mediatek,adsp_intc";
70			interrupt-controller;
71			#interrupt-cells = <3>;
72			reg = <0x1a014010 4>;
73			status-reg = <0x1a014008>;
74			mask = <0x000000c0>;
75			interrupts = <2 0 0>;
76			interrupt-parent = <&core_intc>;
77		};
78
79		ostimer64: ostimer64@1a00b080 {
80			compatible = "mediatek,ostimer64";
81			reg = <0x1a00b080 28>;
82		};
83
84		ostimer0: ostimer@1a00b000 {
85			compatible = "mediatek,ostimer";
86			reg = <0x1a00b000 16>;
87			interrupt-parent = <&intc_g1>;
88			interrupts = <8 0 0>;
89		};
90
91		mbox0: mbox@1a360100 {
92			compatible = "mediatek,mbox";
93			reg = <0x1a360100 16>;
94			interrupt-parent = <&intc_g2>;
95			interrupts = <6 0 0>;
96		};
97
98		mbox1: mbox@1a370100 {
99			compatible = "mediatek,mbox";
100			reg = <0x1a370100 16>;
101			interrupt-parent = <&intc_g2>;
102			interrupts = <7 0 0>;
103		};
104	}; /* soc */
105
106	chosen { };
107	aliases { };
108
109};
110