Lines Matching +full:0 +full:x90000000
57 reg = <0xd0000000 DT_SIZE_M(16)>;
65 reg = <0x90000000 DT_SIZE_M(64)>;
75 #phy-cells = <0>;
128 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
135 pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_ph14>;
142 pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
149 reg = <0x38>;
150 int-gpios = <&gpioh 2 0>;
155 pinctrl-0 = <&spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15 &spi2_nss_pi0>;
162 pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
164 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
171 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
189 mode-register = <0x220>;
190 refresh-rate = <0x603>;
207 pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
216 pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_pj2
234 de-active = <0>;
235 pixelclk-active = <0>;
236 hsync-active = <0>;
237 vsync-active = <0>;
245 def-back-color-red = <0xFF>;
246 def-back-color-green = <0xFF>;
247 def-back-color-blue = <0xFF>;
251 pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pg6
263 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
274 partition@0 {
276 reg = <0x00000000 DT_SIZE_M(4)>;