Lines Matching +full:0 +full:x90000000
40 reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
47 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
100 pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
107 pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
114 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
125 pinctrl-0 = <&tim1_ch1_pa8>;
133 pinctrl-0 = <ð_ref_clk_pa1
151 pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
156 reg = <0x01>;
167 pinctrl-0 = <
184 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
195 storage_partition: partition@0 {
196 reg = <0x0 DT_SIZE_M(64)>;
203 reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
211 pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
217 pinctrl-0 = <&spi2_nss_pb4 &spi2_mosi_pb15 &spi2_miso_pi2 &spi2_sck_pd3>;
223 pinctrl-0 = <&fdcan1_tx_ph13 &fdcan1_rx_ph14>;
225 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
235 pinctrl-0 = <&fdcan2_tx_pb13 &fdcan2_rx_pb5>;
237 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
246 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
264 mode-register = <0x220>;
265 refresh-rate = <0x603>;