| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_device.c | 126 struct amdgpu_device *adev = ddev->dev_private; in amdgpu_device_get_pcie_replay_count() local
127 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); in amdgpu_device_get_pcie_replay_count()
135 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
147 struct amdgpu_device *adev = dev->dev_private; in amdgpu_device_is_px() local
149 if (adev->flags & AMD_IS_PX) in amdgpu_device_is_px()
166 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, in amdgpu_mm_rreg() argument
171 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) in amdgpu_mm_rreg()
172 return amdgpu_virt_kiq_rreg(adev, reg); in amdgpu_mm_rreg()
174 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) in amdgpu_mm_rreg()
175 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); in amdgpu_mm_rreg()
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| D | soc15.c | 90 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
94 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
95 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
97 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
101 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
105 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
109 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
110 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
112 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
117 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
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| D | gmc_v9_0.c | 201 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, in gmc_v9_0_ecc_interrupt_state() argument
246 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, in gmc_v9_0_process_ras_data_cb() argument
250 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); in gmc_v9_0_process_ras_data_cb()
251 if (adev->umc.funcs->query_ras_error_count) in gmc_v9_0_process_ras_data_cb()
252 adev->umc.funcs->query_ras_error_count(adev, err_data); in gmc_v9_0_process_ras_data_cb()
256 if (adev->umc.funcs->query_ras_error_address) in gmc_v9_0_process_ras_data_cb()
257 adev->umc.funcs->query_ras_error_address(adev, err_data); in gmc_v9_0_process_ras_data_cb()
261 amdgpu_ras_reset_gpu(adev, 0); in gmc_v9_0_process_ras_data_cb()
266 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, in gmc_v9_0_process_ecc_irq() argument
270 struct ras_common_if *ras_if = adev->gmc.umc_ras_if; in gmc_v9_0_process_ecc_irq()
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| D | nv.c | 62 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
66 address = adev->nbio_funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
67 data = adev->nbio_funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
69 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in nv_pcie_rreg()
73 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in nv_pcie_rreg()
77 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
81 address = adev->nbio_funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
82 data = adev->nbio_funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
84 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in nv_pcie_wreg()
89 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in nv_pcie_wreg()
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| D | vi.c | 85 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
98 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
110 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
115 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_rreg()
122 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_smc_wreg() argument
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| D | gmc_v10_0.c | 58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v10_0_vm_fault_interrupt_state() argument
84 hub = &adev->vmhub[AMDGPU_MMHUB_0]; in gmc_v10_0_vm_fault_interrupt_state()
93 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; in gmc_v10_0_vm_fault_interrupt_state()
103 hub = &adev->vmhub[AMDGPU_MMHUB_0]; in gmc_v10_0_vm_fault_interrupt_state()
112 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; in gmc_v10_0_vm_fault_interrupt_state()
127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, in gmc_v10_0_process_interrupt() argument
131 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v10_0_process_interrupt()
138 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
155 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); in gmc_v10_0_process_interrupt()
157 dev_err(adev->dev, in gmc_v10_0_process_interrupt()
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| D | amdgpu_acp.c | 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_sw_init() local
100 adev->acp.parent = adev->dev; in acp_sw_init()
102 adev->acp.cgs_device = in acp_sw_init()
103 amdgpu_cgs_create_device(adev); in acp_sw_init()
104 if (!adev->acp.cgs_device) in acp_sw_init()
112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_sw_fini() local
114 if (adev->acp.cgs_device) in acp_sw_fini()
115 amdgpu_cgs_destroy_device(adev->acp.cgs_device); in acp_sw_fini()
121 void *adev; member
128 struct amdgpu_device *adev; in acp_poweroff() local
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| D | amdgpu_gfx.c | 37 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, in amdgpu_gfx_mec_queue_to_bit() argument
42 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
43 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
44 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
50 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit, in amdgpu_gfx_bit_to_mec_queue() argument
53 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_bit_to_mec_queue()
54 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_mec_queue()
55 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_mec_queue()
56 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_mec_queue()
57 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_mec_queue()
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| D | amdgpu_pm.c | 43 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
85 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) in amdgpu_pm_acpi_event_handler() argument
87 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
88 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
90 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
92 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
93 if (adev->powerplay.pp_funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
94 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
95 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
99 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, in amdgpu_dpm_read_sensor() argument
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| D | amdgpu_rlc.c | 37 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev) in amdgpu_gfx_rlc_enter_safe_mode() argument
39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
46 if (adev->cg_flags & in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
61 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev) in amdgpu_gfx_rlc_exit_safe_mode() argument
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
70 if (adev->cg_flags & in amdgpu_gfx_rlc_exit_safe_mode()
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| D | amdgpu_dpm.h | 256 #define amdgpu_dpm_pre_set_power_state(adev) \ argument
257 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
259 #define amdgpu_dpm_set_power_state(adev) \ argument
260 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
262 #define amdgpu_dpm_post_set_power_state(adev) \ argument
263 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
265 #define amdgpu_dpm_display_configuration_changed(adev) \ argument
266 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
268 #define amdgpu_dpm_print_power_state(adev, ps) \ argument
269 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
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| D | amdgpu_gart.c | 72 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_init() argument
74 struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page; in amdgpu_gart_dummy_page_init()
76 if (adev->dummy_page_addr) in amdgpu_gart_dummy_page_init()
78 adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0, in amdgpu_gart_dummy_page_init()
80 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) { in amdgpu_gart_dummy_page_init()
81 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); in amdgpu_gart_dummy_page_init()
82 adev->dummy_page_addr = 0; in amdgpu_gart_dummy_page_init()
95 static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_fini() argument
97 if (!adev->dummy_page_addr) in amdgpu_gart_dummy_page_fini()
99 pci_unmap_page(adev->pdev, adev->dummy_page_addr, in amdgpu_gart_dummy_page_fini()
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| D | vega20_reg_init.c | 30 int vega20_reg_base_init(struct amdgpu_device *adev) in vega20_reg_base_init() argument
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
43 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
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| D | mxgpu_ai.c | 35 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev) in xgpu_ai_mailbox_send_ack() argument
40 static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val) in xgpu_ai_mailbox_set_valid() argument
54 static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev) in xgpu_ai_mailbox_peek_msg() argument
61 static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev, in xgpu_ai_mailbox_rcv_msg() argument
71 xgpu_ai_mailbox_send_ack(adev); in xgpu_ai_mailbox_rcv_msg()
76 static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) { in xgpu_ai_peek_ack() argument
80 static int xgpu_ai_poll_ack(struct amdgpu_device *adev) in xgpu_ai_poll_ack() argument
99 static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event) in xgpu_ai_poll_msg() argument
104 r = xgpu_ai_mailbox_rcv_msg(adev, event); in xgpu_ai_poll_msg()
117 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev, in xgpu_ai_mailbox_trans_msg() argument
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| D | amdgpu_irq.c | 85 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, in amdgpu_hotplug_work_func() local
87 struct drm_device *dev = adev->ddev; in amdgpu_hotplug_work_func()
106 void amdgpu_irq_disable_all(struct amdgpu_device *adev) in amdgpu_irq_disable_all() argument
112 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
114 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
118 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all()
125 r = src->funcs->set(adev, src, k, in amdgpu_irq_disable_all()
133 spin_unlock_irqrestore(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
150 struct amdgpu_device *adev = dev->dev_private; in amdgpu_irq_handler() local
153 ret = amdgpu_ih_process(adev, &adev->irq.ih); in amdgpu_irq_handler()
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| D | amdgpu_cgs.c | 36 struct amdgpu_device *adev; member
40 struct amdgpu_device *adev = \
41 ((struct amdgpu_cgs_device *)cgs_device)->adev
142 if (adev->asic_type >= CHIP_TOPAZ) in fw_type_convert()
167 fw_version = adev->sdma.instance[0].fw_version; in amdgpu_get_firmware_version()
170 fw_version = adev->sdma.instance[1].fw_version; in amdgpu_get_firmware_version()
173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
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| D | amdgpu_amdkfd.c | 64 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) in amdgpu_amdkfd_device_probe() argument
68 switch (adev->asic_type) { in amdgpu_amdkfd_device_probe()
99 dev_info(adev->dev, "kfd not supported on this ASIC\n"); in amdgpu_amdkfd_device_probe()
103 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, in amdgpu_amdkfd_device_probe()
104 adev->pdev, kfd2kgd); in amdgpu_amdkfd_device_probe()
106 if (adev->kfd.dev) in amdgpu_amdkfd_device_probe()
107 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; in amdgpu_amdkfd_device_probe()
123 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, in amdgpu_doorbell_get_kfd_info() argument
132 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { in amdgpu_doorbell_get_kfd_info()
133 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
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| D | vega10_reg_init.c | 30 int vega10_reg_base_init(struct amdgpu_device *adev) in vega10_reg_base_init() argument
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
43 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
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| D | cik.c | 76 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) in cik_pcie_rreg() argument
81 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
85 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
89 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_pcie_wreg() argument
93 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
101 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) in cik_smc_rreg() argument
106 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cik_smc_rreg()
109 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cik_smc_rreg()
113 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_smc_wreg() argument
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| D | kv_dpm.c | 46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53 static void kv_enable_new_levels(struct amdgpu_device *adev);
54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
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| D | gmc_v6_0.c | 44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
75 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) in gmc_v6_0_mc_stop() argument
79 gmc_v6_0_wait_for_idle((void *)adev); in gmc_v6_0_mc_stop()
95 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) in gmc_v6_0_mc_resume() argument
109 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) in gmc_v6_0_init_microcode() argument
118 switch (adev->asic_type) { in gmc_v6_0_init_microcode()
145 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v6_0_init_microcode()
149 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v6_0_init_microcode()
153 dev_err(adev->dev, in gmc_v6_0_init_microcode()
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| D | amdgpu.h | 96 struct amdgpu_device *adev; member
261 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
263 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
265 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
291 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
296 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
299 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
305 bool amdgpu_get_bios(struct amdgpu_device *adev);
306 bool amdgpu_read_bios(struct amdgpu_device *adev);
386 struct amdgpu_device *adev; member
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| D | amdgpu_xgmi.c | 80 static int amdgpu_xgmi_sysfs_create(struct amdgpu_device *adev, in amdgpu_xgmi_sysfs_create() argument
88 hive->kobj = kobject_create_and_add("xgmi_hive_info", &adev->dev->kobj); in amdgpu_xgmi_sysfs_create()
90 dev_err(adev->dev, "XGMI: Failed to allocate sysfs entry!\n"); in amdgpu_xgmi_sysfs_create()
105 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_hive_id\n"); in amdgpu_xgmi_sysfs_create()
114 static void amdgpu_xgmi_sysfs_destroy(struct amdgpu_device *adev, in amdgpu_xgmi_sysfs_destroy() argument
128 struct amdgpu_device *adev = ddev->dev_private; in amdgpu_xgmi_show_device_id() local
130 return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.xgmi.node_id); in amdgpu_xgmi_show_device_id()
140 struct amdgpu_device *adev = ddev->dev_private; in amdgpu_xgmi_show_error() local
148 fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_ctl_in); in amdgpu_xgmi_show_error()
152 fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_status_in); in amdgpu_xgmi_show_error()
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| D | amdgpu_bios.c | 90 static bool igp_read_bios_from_vram(struct amdgpu_device *adev) in igp_read_bios_from_vram() argument
96 if (!(adev->flags & AMD_IS_APU)) in igp_read_bios_from_vram()
97 if (amdgpu_device_need_post(adev)) in igp_read_bios_from_vram()
100 adev->bios = NULL; in igp_read_bios_from_vram()
101 vram_base = pci_resource_start(adev->pdev, 0); in igp_read_bios_from_vram()
107 adev->bios = kmalloc(size, GFP_KERNEL); in igp_read_bios_from_vram()
108 if (!adev->bios) { in igp_read_bios_from_vram()
112 adev->bios_size = size; in igp_read_bios_from_vram()
113 memcpy_fromio(adev->bios, bios, size); in igp_read_bios_from_vram()
116 if (!check_atom_bios(adev->bios, size)) { in igp_read_bios_from_vram()
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| D | gmc_v7_0.c | 53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) in gmc_v7_0_init_golden_registers() argument
76 switch (adev->asic_type) { in gmc_v7_0_init_golden_registers()
78 amdgpu_device_program_register_sequence(adev, in gmc_v7_0_init_golden_registers()
81 amdgpu_device_program_register_sequence(adev, in gmc_v7_0_init_golden_registers()
90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) in gmc_v7_0_mc_stop() argument
94 gmc_v7_0_wait_for_idle((void *)adev); in gmc_v7_0_mc_stop()
109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) in gmc_v7_0_mc_resume() argument
132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) in gmc_v7_0_init_microcode() argument
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