Lines Matching refs:adev
46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53 static void kv_enable_new_levels(struct amdgpu_device *adev);
54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
58 static int kv_force_dpm_highest(struct amdgpu_device *adev);
59 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
60 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
63 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
65 static int kv_init_fps_limits(struct amdgpu_device *adev);
67 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
68 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
71 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev, in kv_convert_vid2_to_vid7() argument
76 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
93 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev, in kv_convert_vid7_to_vid2() argument
98 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
117 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable) in sumo_take_smu_control() argument
136 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev, in sumo_construct_sclk_voltage_mapping_table() argument
158 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev, in sumo_construct_vid_mapping_table() argument
377 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev) in kv_get_pi() argument
379 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
385 static void kv_program_local_cac_table(struct amdgpu_device *adev,
410 static int kv_program_pt_config_registers(struct amdgpu_device *adev, in kv_program_pt_config_registers() argument
459 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable) in kv_do_enable_didt() argument
461 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt()
501 static int kv_enable_didt(struct amdgpu_device *adev, bool enable) in kv_enable_didt() argument
503 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt()
510 amdgpu_gfx_rlc_enter_safe_mode(adev); in kv_enable_didt()
513 ret = kv_program_pt_config_registers(adev, didt_config_kv); in kv_enable_didt()
515 amdgpu_gfx_rlc_exit_safe_mode(adev); in kv_enable_didt()
520 kv_do_enable_didt(adev, enable); in kv_enable_didt()
522 amdgpu_gfx_rlc_exit_safe_mode(adev); in kv_enable_didt()
529 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
531 struct kv_power_info *pi = kv_get_pi(adev);
536 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
540 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
544 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
548 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
552 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
556 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
561 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable) in kv_enable_smc_cac() argument
563 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac()
568 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac); in kv_enable_smc_cac()
574 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac); in kv_enable_smc_cac()
582 static int kv_process_firmware_header(struct amdgpu_device *adev) in kv_process_firmware_header() argument
584 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header()
588 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + in kv_process_firmware_header()
595 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + in kv_process_firmware_header()
605 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev) in kv_enable_dpm_voltage_scaling() argument
607 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling()
612 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_enable_dpm_voltage_scaling()
621 static int kv_set_dpm_interval(struct amdgpu_device *adev) in kv_set_dpm_interval() argument
623 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval()
628 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_set_dpm_interval()
637 static int kv_set_dpm_boot_state(struct amdgpu_device *adev) in kv_set_dpm_boot_state() argument
639 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state()
642 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_set_dpm_boot_state()
651 static void kv_program_vc(struct amdgpu_device *adev) in kv_program_vc() argument
656 static void kv_clear_vc(struct amdgpu_device *adev) in kv_clear_vc() argument
661 static int kv_set_divider_value(struct amdgpu_device *adev, in kv_set_divider_value() argument
664 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value()
668 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_set_divider_value()
679 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev, in kv_convert_8bit_index_to_voltage() argument
685 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev, in kv_convert_2bit_index_to_voltage() argument
688 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage()
689 u32 vid_8bit = kv_convert_vid2_to_vid7(adev, in kv_convert_2bit_index_to_voltage()
693 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit); in kv_convert_2bit_index_to_voltage()
697 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid) in kv_set_vid() argument
699 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid()
703 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid)); in kv_set_vid()
708 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at) in kv_set_at() argument
710 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at()
717 static void kv_dpm_power_level_enable(struct amdgpu_device *adev, in kv_dpm_power_level_enable() argument
720 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable()
725 static void kv_start_dpm(struct amdgpu_device *adev) in kv_start_dpm() argument
732 amdgpu_kv_smc_dpm_enable(adev, true); in kv_start_dpm()
735 static void kv_stop_dpm(struct amdgpu_device *adev) in kv_stop_dpm() argument
737 amdgpu_kv_smc_dpm_enable(adev, false); in kv_stop_dpm()
740 static void kv_start_am(struct amdgpu_device *adev) in kv_start_am() argument
751 static void kv_reset_am(struct amdgpu_device *adev) in kv_reset_am() argument
761 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze) in kv_freeze_sclk_dpm() argument
763 return amdgpu_kv_notify_message_to_smu(adev, freeze ? in kv_freeze_sclk_dpm()
767 static int kv_force_lowest_valid(struct amdgpu_device *adev) in kv_force_lowest_valid() argument
769 return kv_force_dpm_lowest(adev); in kv_force_lowest_valid()
772 static int kv_unforce_levels(struct amdgpu_device *adev) in kv_unforce_levels() argument
774 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_unforce_levels()
775 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel); in kv_unforce_levels()
777 return kv_set_enabled_levels(adev); in kv_unforce_levels()
780 static int kv_update_sclk_t(struct amdgpu_device *adev) in kv_update_sclk_t() argument
782 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t()
789 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_sclk_t()
798 static int kv_program_bootup_state(struct amdgpu_device *adev) in kv_program_bootup_state() argument
800 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state()
803 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
812 kv_dpm_power_level_enable(adev, i, true); in kv_program_bootup_state()
826 kv_dpm_power_level_enable(adev, i, true); in kv_program_bootup_state()
831 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev) in kv_enable_auto_thermal_throttling() argument
833 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling()
838 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_enable_auto_thermal_throttling()
847 static int kv_upload_dpm_settings(struct amdgpu_device *adev) in kv_upload_dpm_settings() argument
849 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings()
852 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_upload_dpm_settings()
862 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_upload_dpm_settings()
876 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk) in kv_get_clk_bypass() argument
878 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass()
901 static int kv_populate_uvd_table(struct amdgpu_device *adev) in kv_populate_uvd_table() argument
903 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table()
905 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
924 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); in kv_populate_uvd_table()
926 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk); in kv_populate_uvd_table()
928 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_uvd_table()
934 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_uvd_table()
943 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
953 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
961 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
972 static int kv_populate_vce_table(struct amdgpu_device *adev) in kv_populate_vce_table() argument
974 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table()
978 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
994 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); in kv_populate_vce_table()
996 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_vce_table()
1005 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1016 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1025 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1035 static int kv_populate_samu_table(struct amdgpu_device *adev) in kv_populate_samu_table() argument
1037 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table()
1039 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1057 (u8)kv_get_clk_bypass(adev, table->entries[i].clk); in kv_populate_samu_table()
1059 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_samu_table()
1068 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1079 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1088 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1101 static int kv_populate_acp_table(struct amdgpu_device *adev) in kv_populate_acp_table() argument
1103 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table()
1105 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1118 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_acp_table()
1127 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1138 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1147 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1159 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev) in kv_calculate_dfs_bypass_settings() argument
1161 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings()
1164 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1209 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable) in kv_enable_ulv() argument
1211 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_ulv()
1215 static void kv_reset_acp_boot_level(struct amdgpu_device *adev) in kv_reset_acp_boot_level() argument
1217 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level()
1222 static void kv_update_current_ps(struct amdgpu_device *adev, in kv_update_current_ps() argument
1226 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps()
1231 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1234 static void kv_update_requested_ps(struct amdgpu_device *adev, in kv_update_requested_ps() argument
1238 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps()
1243 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_enable_bapm() local
1249 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm()
1253 ret = amdgpu_kv_smc_bapm_enable(adev, enable); in kv_dpm_enable_bapm()
1259 static int kv_dpm_enable(struct amdgpu_device *adev) in kv_dpm_enable() argument
1261 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable()
1264 ret = kv_process_firmware_header(adev); in kv_dpm_enable()
1269 kv_init_fps_limits(adev); in kv_dpm_enable()
1270 kv_init_graphics_levels(adev); in kv_dpm_enable()
1271 ret = kv_program_bootup_state(adev); in kv_dpm_enable()
1276 kv_calculate_dfs_bypass_settings(adev); in kv_dpm_enable()
1277 ret = kv_upload_dpm_settings(adev); in kv_dpm_enable()
1282 ret = kv_populate_uvd_table(adev); in kv_dpm_enable()
1287 ret = kv_populate_vce_table(adev); in kv_dpm_enable()
1292 ret = kv_populate_samu_table(adev); in kv_dpm_enable()
1297 ret = kv_populate_acp_table(adev); in kv_dpm_enable()
1302 kv_program_vc(adev); in kv_dpm_enable()
1304 kv_initialize_hardware_cac_manager(adev); in kv_dpm_enable()
1306 kv_start_am(adev); in kv_dpm_enable()
1308 ret = kv_enable_auto_thermal_throttling(adev); in kv_dpm_enable()
1314 ret = kv_enable_dpm_voltage_scaling(adev); in kv_dpm_enable()
1319 ret = kv_set_dpm_interval(adev); in kv_dpm_enable()
1324 ret = kv_set_dpm_boot_state(adev); in kv_dpm_enable()
1329 ret = kv_enable_ulv(adev, true); in kv_dpm_enable()
1334 kv_start_dpm(adev); in kv_dpm_enable()
1335 ret = kv_enable_didt(adev, true); in kv_dpm_enable()
1340 ret = kv_enable_smc_cac(adev, true); in kv_dpm_enable()
1346 kv_reset_acp_boot_level(adev); in kv_dpm_enable()
1348 ret = amdgpu_kv_smc_bapm_enable(adev, false); in kv_dpm_enable()
1354 if (adev->irq.installed && in kv_dpm_enable()
1355 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { in kv_dpm_enable()
1356 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX); in kv_dpm_enable()
1361 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1363 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1370 static void kv_dpm_disable(struct amdgpu_device *adev) in kv_dpm_disable() argument
1372 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_disable()
1374 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1376 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1379 amdgpu_kv_smc_bapm_enable(adev, false); in kv_dpm_disable()
1381 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_disable()
1382 kv_enable_nb_dpm(adev, false); in kv_dpm_disable()
1385 kv_dpm_powergate_acp(adev, false); in kv_dpm_disable()
1386 kv_dpm_powergate_samu(adev, false); in kv_dpm_disable()
1388 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); in kv_dpm_disable()
1390 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); in kv_dpm_disable()
1392 kv_enable_smc_cac(adev, false); in kv_dpm_disable()
1393 kv_enable_didt(adev, false); in kv_dpm_disable()
1394 kv_clear_vc(adev); in kv_dpm_disable()
1395 kv_stop_dpm(adev); in kv_dpm_disable()
1396 kv_enable_ulv(adev, false); in kv_dpm_disable()
1397 kv_reset_am(adev); in kv_dpm_disable()
1399 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_disable()
1403 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1406 struct kv_power_info *pi = kv_get_pi(adev);
1408 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1412 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1415 struct kv_power_info *pi = kv_get_pi(adev);
1417 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1422 static void kv_init_sclk_t(struct amdgpu_device *adev) in kv_init_sclk_t() argument
1424 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t()
1429 static int kv_init_fps_limits(struct amdgpu_device *adev) in kv_init_fps_limits() argument
1431 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits()
1439 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_init_fps_limits()
1448 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_init_fps_limits()
1458 static void kv_init_powergate_state(struct amdgpu_device *adev) in kv_init_powergate_state() argument
1460 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state()
1469 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_uvd_dpm() argument
1471 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_uvd_dpm()
1475 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_vce_dpm() argument
1477 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_vce_dpm()
1481 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_samu_dpm() argument
1483 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_samu_dpm()
1487 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_acp_dpm() argument
1489 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_acp_dpm()
1493 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in kv_update_uvd_dpm() argument
1495 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm()
1497 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1513 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_uvd_dpm()
1521 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_uvd_dpm()
1526 return kv_enable_uvd_dpm(adev, !gate); in kv_update_uvd_dpm()
1529 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) in kv_get_vce_boot_level() argument
1533 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
1543 static int kv_update_vce_dpm(struct amdgpu_device *adev, in kv_update_vce_dpm() argument
1547 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm()
1549 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_update_vce_dpm()
1556 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1558 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_vce_dpm()
1568 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_vce_dpm()
1571 kv_enable_vce_dpm(adev, true); in kv_update_vce_dpm()
1573 kv_enable_vce_dpm(adev, false); in kv_update_vce_dpm()
1579 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate) in kv_update_samu_dpm() argument
1581 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm()
1583 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_update_samu_dpm()
1592 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_samu_dpm()
1602 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_samu_dpm()
1607 return kv_enable_samu_dpm(adev, !gate); in kv_update_samu_dpm()
1610 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev) in kv_get_acp_boot_level() argument
1614 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_get_acp_boot_level()
1627 static void kv_update_acp_boot_level(struct amdgpu_device *adev) in kv_update_acp_boot_level() argument
1629 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level()
1633 acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_boot_level()
1636 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_acp_boot_level()
1643 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate) in kv_update_acp_dpm() argument
1645 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm()
1647 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_update_acp_dpm()
1654 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1656 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_acp_dpm()
1666 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_acp_dpm()
1671 return kv_enable_acp_dpm(adev, !gate); in kv_update_acp_dpm()
1676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_powergate_uvd() local
1677 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd()
1684 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1686 kv_update_uvd_dpm(adev, gate); in kv_dpm_powergate_uvd()
1689 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); in kv_dpm_powergate_uvd()
1693 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); in kv_dpm_powergate_uvd()
1695 kv_update_uvd_dpm(adev, gate); in kv_dpm_powergate_uvd()
1697 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1704 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_powergate_vce() local
1705 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce()
1712 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_dpm_powergate_vce()
1714 kv_enable_vce_dpm(adev, false); in kv_dpm_powergate_vce()
1716 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); in kv_dpm_powergate_vce()
1719 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); in kv_dpm_powergate_vce()
1720 kv_enable_vce_dpm(adev, true); in kv_dpm_powergate_vce()
1722 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_dpm_powergate_vce()
1728 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_samu() argument
1730 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu()
1738 kv_update_samu_dpm(adev, true); in kv_dpm_powergate_samu()
1740 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF); in kv_dpm_powergate_samu()
1743 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON); in kv_dpm_powergate_samu()
1744 kv_update_samu_dpm(adev, false); in kv_dpm_powergate_samu()
1748 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_acp() argument
1750 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp()
1755 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_dpm_powergate_acp()
1761 kv_update_acp_dpm(adev, true); in kv_dpm_powergate_acp()
1763 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF); in kv_dpm_powergate_acp()
1766 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON); in kv_dpm_powergate_acp()
1767 kv_update_acp_dpm(adev, false); in kv_dpm_powergate_acp()
1771 static void kv_set_valid_clock_range(struct amdgpu_device *adev, in kv_set_valid_clock_range() argument
1775 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range()
1778 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1833 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev, in kv_update_dfs_bypass_settings() argument
1837 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings()
1844 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_dfs_bypass_settings()
1856 static int kv_enable_nb_dpm(struct amdgpu_device *adev, in kv_enable_nb_dpm() argument
1859 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm()
1864 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable); in kv_enable_nb_dpm()
1870 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable); in kv_enable_nb_dpm()
1883 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_force_performance_level() local
1886 ret = kv_force_dpm_highest(adev); in kv_dpm_force_performance_level()
1890 ret = kv_force_dpm_lowest(adev); in kv_dpm_force_performance_level()
1894 ret = kv_unforce_levels(adev); in kv_dpm_force_performance_level()
1899 adev->pm.dpm.forced_level = level; in kv_dpm_force_performance_level()
1906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_pre_set_power_state() local
1907 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state()
1908 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in kv_dpm_pre_set_power_state()
1911 kv_update_requested_ps(adev, new_ps); in kv_dpm_pre_set_power_state()
1913 kv_apply_state_adjust_rules(adev, in kv_dpm_pre_set_power_state()
1922 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_set_power_state() local
1923 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state()
1929 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power); in kv_dpm_set_power_state()
1936 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_dpm_set_power_state()
1938 kv_set_valid_clock_range(adev, new_ps); in kv_dpm_set_power_state()
1939 kv_update_dfs_bypass_settings(adev, new_ps); in kv_dpm_set_power_state()
1940 ret = kv_calculate_ds_divider(adev); in kv_dpm_set_power_state()
1945 kv_calculate_nbps_level_settings(adev); in kv_dpm_set_power_state()
1946 kv_calculate_dpm_settings(adev); in kv_dpm_set_power_state()
1947 kv_force_lowest_valid(adev); in kv_dpm_set_power_state()
1948 kv_enable_new_levels(adev); in kv_dpm_set_power_state()
1949 kv_upload_dpm_settings(adev); in kv_dpm_set_power_state()
1950 kv_program_nbps_index_settings(adev, new_ps); in kv_dpm_set_power_state()
1951 kv_unforce_levels(adev); in kv_dpm_set_power_state()
1952 kv_set_enabled_levels(adev); in kv_dpm_set_power_state()
1953 kv_force_lowest_valid(adev); in kv_dpm_set_power_state()
1954 kv_unforce_levels(adev); in kv_dpm_set_power_state()
1956 ret = kv_update_vce_dpm(adev, new_ps, old_ps); in kv_dpm_set_power_state()
1961 kv_update_sclk_t(adev); in kv_dpm_set_power_state()
1962 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_set_power_state()
1963 kv_enable_nb_dpm(adev, true); in kv_dpm_set_power_state()
1967 kv_set_valid_clock_range(adev, new_ps); in kv_dpm_set_power_state()
1968 kv_update_dfs_bypass_settings(adev, new_ps); in kv_dpm_set_power_state()
1969 ret = kv_calculate_ds_divider(adev); in kv_dpm_set_power_state()
1974 kv_calculate_nbps_level_settings(adev); in kv_dpm_set_power_state()
1975 kv_calculate_dpm_settings(adev); in kv_dpm_set_power_state()
1976 kv_freeze_sclk_dpm(adev, true); in kv_dpm_set_power_state()
1977 kv_upload_dpm_settings(adev); in kv_dpm_set_power_state()
1978 kv_program_nbps_index_settings(adev, new_ps); in kv_dpm_set_power_state()
1979 kv_freeze_sclk_dpm(adev, false); in kv_dpm_set_power_state()
1980 kv_set_enabled_levels(adev); in kv_dpm_set_power_state()
1981 ret = kv_update_vce_dpm(adev, new_ps, old_ps); in kv_dpm_set_power_state()
1986 kv_update_acp_boot_level(adev); in kv_dpm_set_power_state()
1987 kv_update_sclk_t(adev); in kv_dpm_set_power_state()
1988 kv_enable_nb_dpm(adev, true); in kv_dpm_set_power_state()
1997 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_post_set_power_state() local
1998 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state()
2001 kv_update_current_ps(adev, new_ps); in kv_dpm_post_set_power_state()
2004 static void kv_dpm_setup_asic(struct amdgpu_device *adev) in kv_dpm_setup_asic() argument
2006 sumo_take_smu_control(adev, true); in kv_dpm_setup_asic()
2007 kv_init_powergate_state(adev); in kv_dpm_setup_asic()
2008 kv_init_sclk_t(adev); in kv_dpm_setup_asic()
2012 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2014 struct kv_power_info *pi = kv_get_pi(adev);
2016 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2017 kv_force_lowest_valid(adev);
2018 kv_init_graphics_levels(adev);
2019 kv_program_bootup_state(adev);
2020 kv_upload_dpm_settings(adev);
2021 kv_force_lowest_valid(adev);
2022 kv_unforce_levels(adev);
2024 kv_init_graphics_levels(adev);
2025 kv_program_bootup_state(adev);
2026 kv_freeze_sclk_dpm(adev, true);
2027 kv_upload_dpm_settings(adev);
2028 kv_freeze_sclk_dpm(adev, false);
2029 kv_set_enabled_level(adev, pi->graphics_boot_level);
2034 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev, in kv_construct_max_power_limits_table() argument
2037 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table()
2044 kv_convert_2bit_index_to_voltage(adev, in kv_construct_max_power_limits_table()
2051 static void kv_patch_voltage_values(struct amdgpu_device *adev) in kv_patch_voltage_values() argument
2055 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_patch_voltage_values()
2057 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_patch_voltage_values()
2059 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_patch_voltage_values()
2061 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_patch_voltage_values()
2066 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2073 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2080 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2087 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2093 static void kv_construct_boot_state(struct amdgpu_device *adev) in kv_construct_boot_state() argument
2095 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state()
2107 static int kv_force_dpm_highest(struct amdgpu_device *adev) in kv_force_dpm_highest() argument
2112 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); in kv_force_dpm_highest()
2121 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_highest()
2122 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); in kv_force_dpm_highest()
2124 return kv_set_enabled_level(adev, i); in kv_force_dpm_highest()
2127 static int kv_force_dpm_lowest(struct amdgpu_device *adev) in kv_force_dpm_lowest() argument
2132 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); in kv_force_dpm_lowest()
2141 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_lowest()
2142 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); in kv_force_dpm_lowest()
2144 return kv_set_enabled_level(adev, i); in kv_force_dpm_lowest()
2147 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, in kv_get_sleep_divider_id_from_clock() argument
2150 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock()
2170 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit) in kv_get_high_voltage_limit() argument
2172 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit()
2174 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2180 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <= in kv_get_high_voltage_limit()
2192 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <= in kv_get_high_voltage_limit()
2204 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, in kv_apply_state_adjust_rules() argument
2209 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules()
2215 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2218 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2221 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2222 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2248 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in kv_apply_state_adjust_rules()
2249 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in kv_apply_state_adjust_rules()
2263 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { in kv_apply_state_adjust_rules()
2264 kv_get_high_voltage_limit(adev, &limit); in kv_apply_state_adjust_rules()
2275 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { in kv_apply_state_adjust_rules()
2276 kv_get_high_voltage_limit(adev, &limit); in kv_apply_state_adjust_rules()
2297 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_apply_state_adjust_rules()
2310 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2320 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev, in kv_dpm_power_level_enabled_for_throttle() argument
2323 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle()
2328 static int kv_calculate_ds_divider(struct amdgpu_device *adev) in kv_calculate_ds_divider() argument
2330 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider()
2339 kv_get_sleep_divider_id_from_clock(adev, in kv_calculate_ds_divider()
2346 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev) in kv_calculate_nbps_level_settings() argument
2348 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings()
2352 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2358 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_calculate_nbps_level_settings()
2369 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2400 static int kv_calculate_dpm_settings(struct amdgpu_device *adev) in kv_calculate_dpm_settings() argument
2402 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings()
2414 static void kv_init_graphics_levels(struct amdgpu_device *adev) in kv_init_graphics_levels() argument
2416 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels()
2419 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
2428 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v))) in kv_init_graphics_levels()
2431 kv_set_divider_value(adev, i, table->entries[i].clk); in kv_init_graphics_levels()
2432 vid_2bit = kv_convert_vid7_to_vid2(adev, in kv_init_graphics_levels()
2435 kv_set_vid(adev, i, vid_2bit); in kv_init_graphics_levels()
2436 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2437 kv_dpm_power_level_enabled_for_throttle(adev, i, true); in kv_init_graphics_levels()
2448 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit)) in kv_init_graphics_levels()
2451 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency); in kv_init_graphics_levels()
2452 kv_set_vid(adev, i, table->entries[i].vid_2bit); in kv_init_graphics_levels()
2453 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2454 kv_dpm_power_level_enabled_for_throttle(adev, i, true); in kv_init_graphics_levels()
2460 kv_dpm_power_level_enable(adev, i, false); in kv_init_graphics_levels()
2463 static void kv_enable_new_levels(struct amdgpu_device *adev) in kv_enable_new_levels() argument
2465 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels()
2470 kv_dpm_power_level_enable(adev, i, true); in kv_enable_new_levels()
2474 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level) in kv_set_enabled_level() argument
2478 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_set_enabled_level()
2483 static int kv_set_enabled_levels(struct amdgpu_device *adev) in kv_set_enabled_levels() argument
2485 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels()
2491 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_set_enabled_levels()
2496 static void kv_program_nbps_index_settings(struct amdgpu_device *adev, in kv_program_nbps_index_settings() argument
2500 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings()
2503 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_program_nbps_index_settings()
2520 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, in kv_set_thermal_temperature_range() argument
2543 adev->pm.dpm.thermal.min_temp = low_temp; in kv_set_thermal_temperature_range()
2544 adev->pm.dpm.thermal.max_temp = high_temp; in kv_set_thermal_temperature_range()
2558 static int kv_parse_sys_info_table(struct amdgpu_device *adev) in kv_parse_sys_info_table() argument
2560 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table()
2561 struct amdgpu_mode_info *mode_info = &adev->mode_info; in kv_parse_sys_info_table()
2608 sumo_construct_sclk_voltage_mapping_table(adev, in kv_parse_sys_info_table()
2612 sumo_construct_vid_mapping_table(adev, in kv_parse_sys_info_table()
2616 kv_construct_max_power_limits_table(adev, in kv_parse_sys_info_table()
2617 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in kv_parse_sys_info_table()
2643 static void kv_patch_boot_state(struct amdgpu_device *adev, in kv_patch_boot_state() argument
2646 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state()
2652 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev, in kv_parse_pplib_non_clock_info() argument
2672 adev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2673 kv_patch_boot_state(adev, ps); in kv_parse_pplib_non_clock_info()
2676 adev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2679 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev, in kv_parse_pplib_clock_info() argument
2683 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info()
2701 static int kv_parse_power_table(struct amdgpu_device *adev) in kv_parse_power_table() argument
2703 struct amdgpu_mode_info *mode_info = &adev->mode_info; in kv_parse_power_table()
2723 amdgpu_add_thermal_controller(adev); in kv_parse_power_table()
2735 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in kv_parse_power_table()
2738 if (!adev->pm.dpm.ps) in kv_parse_power_table()
2749 kfree(adev->pm.dpm.ps); in kv_parse_power_table()
2752 adev->pm.dpm.ps[i].ps_priv = ps; in kv_parse_power_table()
2764 kv_parse_pplib_clock_info(adev, in kv_parse_power_table()
2765 &adev->pm.dpm.ps[i], k, in kv_parse_power_table()
2769 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in kv_parse_power_table()
2774 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
2777 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in kv_parse_power_table()
2779 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in kv_parse_power_table()
2784 adev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2785 adev->pm.dpm.vce_states[i].mclk = 0; in kv_parse_power_table()
2791 static int kv_dpm_init(struct amdgpu_device *adev) in kv_dpm_init() argument
2799 adev->pm.dpm.priv = pi; in kv_dpm_init()
2801 ret = amdgpu_get_platform_caps(adev); in kv_dpm_init()
2805 ret = amdgpu_parse_extended_power_table(adev); in kv_dpm_init()
2826 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) in kv_dpm_init()
2840 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2842 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2843 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2844 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2847 ret = kv_parse_sys_info_table(adev); in kv_dpm_init()
2851 kv_patch_voltage_values(adev); in kv_dpm_init()
2852 kv_construct_boot_state(adev); in kv_dpm_init()
2854 ret = kv_parse_power_table(adev); in kv_dpm_init()
2867 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_debugfs_print_current_performance_level() local
2868 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level()
2883 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp); in kv_dpm_debugfs_print_current_performance_level()
2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_print_power_state() local
2906 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index)); in kv_dpm_print_power_state()
2908 amdgpu_dpm_print_ps_status(adev, rps); in kv_dpm_print_power_state()
2911 static void kv_dpm_fini(struct amdgpu_device *adev) in kv_dpm_fini() argument
2915 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in kv_dpm_fini()
2916 kfree(adev->pm.dpm.ps[i].ps_priv); in kv_dpm_fini()
2918 kfree(adev->pm.dpm.ps); in kv_dpm_fini()
2919 kfree(adev->pm.dpm.priv); in kv_dpm_fini()
2920 amdgpu_free_extended_power_table(adev); in kv_dpm_fini()
2930 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_sclk() local
2931 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk()
2942 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_mclk() local
2943 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk()
2953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_temp() local
2969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_early_init() local
2971 adev->powerplay.pp_funcs = &kv_dpm_funcs; in kv_dpm_early_init()
2972 adev->powerplay.pp_handle = adev; in kv_dpm_early_init()
2973 kv_dpm_set_irq_funcs(adev); in kv_dpm_early_init()
2981 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_late_init() local
2983 if (!adev->pm.dpm_enabled) in kv_dpm_late_init()
2986 kv_dpm_powergate_acp(adev, true); in kv_dpm_late_init()
2987 kv_dpm_powergate_samu(adev, true); in kv_dpm_late_init()
2995 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_sw_init() local
2997 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, in kv_dpm_sw_init()
2998 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3002 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, in kv_dpm_sw_init()
3003 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3008 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3009 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3010 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; in kv_dpm_sw_init()
3011 adev->pm.default_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3012 adev->pm.default_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3013 adev->pm.current_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3014 adev->pm.current_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3015 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; in kv_dpm_sw_init()
3020 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in kv_dpm_sw_init()
3021 mutex_lock(&adev->pm.mutex); in kv_dpm_sw_init()
3022 ret = kv_dpm_init(adev); in kv_dpm_sw_init()
3025 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_sw_init()
3027 amdgpu_pm_print_power_states(adev); in kv_dpm_sw_init()
3028 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_init()
3034 kv_dpm_fini(adev); in kv_dpm_sw_init()
3035 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_init()
3042 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_sw_fini() local
3044 flush_work(&adev->pm.dpm.thermal.work); in kv_dpm_sw_fini()
3046 mutex_lock(&adev->pm.mutex); in kv_dpm_sw_fini()
3047 kv_dpm_fini(adev); in kv_dpm_sw_fini()
3048 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_fini()
3056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_hw_init() local
3061 mutex_lock(&adev->pm.mutex); in kv_dpm_hw_init()
3062 kv_dpm_setup_asic(adev); in kv_dpm_hw_init()
3063 ret = kv_dpm_enable(adev); in kv_dpm_hw_init()
3065 adev->pm.dpm_enabled = false; in kv_dpm_hw_init()
3067 adev->pm.dpm_enabled = true; in kv_dpm_hw_init()
3068 mutex_unlock(&adev->pm.mutex); in kv_dpm_hw_init()
3069 amdgpu_pm_compute_clocks(adev); in kv_dpm_hw_init()
3075 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_hw_fini() local
3077 if (adev->pm.dpm_enabled) { in kv_dpm_hw_fini()
3078 mutex_lock(&adev->pm.mutex); in kv_dpm_hw_fini()
3079 kv_dpm_disable(adev); in kv_dpm_hw_fini()
3080 mutex_unlock(&adev->pm.mutex); in kv_dpm_hw_fini()
3088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_suspend() local
3090 if (adev->pm.dpm_enabled) { in kv_dpm_suspend()
3091 mutex_lock(&adev->pm.mutex); in kv_dpm_suspend()
3093 kv_dpm_disable(adev); in kv_dpm_suspend()
3095 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_suspend()
3096 mutex_unlock(&adev->pm.mutex); in kv_dpm_suspend()
3104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_resume() local
3106 if (adev->pm.dpm_enabled) { in kv_dpm_resume()
3108 mutex_lock(&adev->pm.mutex); in kv_dpm_resume()
3109 kv_dpm_setup_asic(adev); in kv_dpm_resume()
3110 ret = kv_dpm_enable(adev); in kv_dpm_resume()
3112 adev->pm.dpm_enabled = false; in kv_dpm_resume()
3114 adev->pm.dpm_enabled = true; in kv_dpm_resume()
3115 mutex_unlock(&adev->pm.mutex); in kv_dpm_resume()
3116 if (adev->pm.dpm_enabled) in kv_dpm_resume()
3117 amdgpu_pm_compute_clocks(adev); in kv_dpm_resume()
3138 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev, in kv_dpm_set_interrupt_state() argument
3186 static int kv_dpm_process_interrupt(struct amdgpu_device *adev, in kv_dpm_process_interrupt() argument
3198 adev->pm.dpm.thermal.high_to_low = false; in kv_dpm_process_interrupt()
3203 adev->pm.dpm.thermal.high_to_low = true; in kv_dpm_process_interrupt()
3211 schedule_work(&adev->pm.dpm.thermal.work); in kv_dpm_process_interrupt()
3247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_check_state_equal() local
3249 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) in kv_check_state_equal()
3283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_read_sensor() local
3284 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_read_sensor()
3306 *((uint32_t *)value) = kv_dpm_get_temp(adev); in kv_dpm_read_sensor()
3378 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev) in kv_dpm_set_irq_funcs() argument
3380 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in kv_dpm_set_irq_funcs()
3381 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; in kv_dpm_set_irq_funcs()