35 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)  in xgpu_ai_mailbox_send_ack()  argument
40 static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)  in xgpu_ai_mailbox_set_valid()  argument
54 static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev)  in xgpu_ai_mailbox_peek_msg()  argument
61 static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev,  in xgpu_ai_mailbox_rcv_msg()  argument
71 	xgpu_ai_mailbox_send_ack(adev);  in xgpu_ai_mailbox_rcv_msg()
76 static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) {  in xgpu_ai_peek_ack()  argument
80 static int xgpu_ai_poll_ack(struct amdgpu_device *adev)  in xgpu_ai_poll_ack()  argument
99 static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)  in xgpu_ai_poll_msg()  argument
104 		r = xgpu_ai_mailbox_rcv_msg(adev, event);  in xgpu_ai_poll_msg()
117 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,  in xgpu_ai_mailbox_trans_msg()  argument
130 		xgpu_ai_mailbox_set_valid(adev, false);  in xgpu_ai_mailbox_trans_msg()
131 		trn = xgpu_ai_peek_ack(adev);  in xgpu_ai_mailbox_trans_msg()
151 	xgpu_ai_mailbox_set_valid(adev, true);  in xgpu_ai_mailbox_trans_msg()
154 	r = xgpu_ai_poll_ack(adev);  in xgpu_ai_mailbox_trans_msg()
158 	xgpu_ai_mailbox_set_valid(adev, false);  in xgpu_ai_mailbox_trans_msg()
161 static int xgpu_ai_get_pp_clk(struct amdgpu_device *adev, u32 type, char *buf)  in xgpu_ai_get_pp_clk()  argument
166         if (!amdgim_is_hwperf(adev) || buf == NULL)  in xgpu_ai_get_pp_clk()
180         mutex_lock(&adev->virt.dpm_mutex);  in xgpu_ai_get_pp_clk()
182         xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0);  in xgpu_ai_get_pp_clk()
184         r = xgpu_ai_poll_msg(adev, IDH_SUCCESS);  in xgpu_ai_get_pp_clk()
185         if (!r && adev->fw_vram_usage.va != NULL) {  in xgpu_ai_get_pp_clk()
189                 size = strnlen((((char *)adev->virt.fw_reserve.p_pf2vf) +  in xgpu_ai_get_pp_clk()
193                         strcpy(buf,((char *)adev->virt.fw_reserve.p_pf2vf + val));  in xgpu_ai_get_pp_clk()
201         r = xgpu_ai_poll_msg(adev, IDH_FAIL);  in xgpu_ai_get_pp_clk()
207         mutex_unlock(&adev->virt.dpm_mutex);  in xgpu_ai_get_pp_clk()
211 static int xgpu_ai_force_dpm_level(struct amdgpu_device *adev, u32 level)  in xgpu_ai_force_dpm_level()  argument
216         if (!amdgim_is_hwperf(adev))  in xgpu_ai_force_dpm_level()
219         mutex_lock(&adev->virt.dpm_mutex);  in xgpu_ai_force_dpm_level()
220         xgpu_ai_mailbox_trans_msg(adev, req, level, 0, 0);  in xgpu_ai_force_dpm_level()
222         r = xgpu_ai_poll_msg(adev, IDH_SUCCESS);  in xgpu_ai_force_dpm_level()
226         r = xgpu_ai_poll_msg(adev, IDH_FAIL);  in xgpu_ai_force_dpm_level()
233         mutex_unlock(&adev->virt.dpm_mutex);  in xgpu_ai_force_dpm_level()
237 static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,  in xgpu_ai_send_access_requests()  argument
242 	xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0);  in xgpu_ai_send_access_requests()
248 		r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);  in xgpu_ai_send_access_requests()
255 			adev->virt.fw_reserve.checksum_key =  in xgpu_ai_send_access_requests()
264 static int xgpu_ai_request_reset(struct amdgpu_device *adev)  in xgpu_ai_request_reset()  argument
266 	return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);  in xgpu_ai_request_reset()
269 static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,  in xgpu_ai_request_full_gpu_access()  argument
275 	return xgpu_ai_send_access_requests(adev, req);  in xgpu_ai_request_full_gpu_access()
278 static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev,  in xgpu_ai_release_full_gpu_access()  argument
285 	r = xgpu_ai_send_access_requests(adev, req);  in xgpu_ai_release_full_gpu_access()
290 static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,  in xgpu_ai_mailbox_ack_irq()  argument
298 static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev,  in xgpu_ai_set_mailbox_ack_irq()  argument
315 	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);  in xgpu_ai_mailbox_flr_work()  local
327 	locked = mutex_trylock(&adev->lock_reset);  in xgpu_ai_mailbox_flr_work()
329 		adev->in_gpu_reset = 1;  in xgpu_ai_mailbox_flr_work()
332 		if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)  in xgpu_ai_mailbox_flr_work()
341 		adev->in_gpu_reset = 0;  in xgpu_ai_mailbox_flr_work()
342 		mutex_unlock(&adev->lock_reset);  in xgpu_ai_mailbox_flr_work()
346 	if (amdgpu_device_should_recover_gpu(adev)  in xgpu_ai_mailbox_flr_work()
347 		&& adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT)  in xgpu_ai_mailbox_flr_work()
348 		amdgpu_device_gpu_recover(adev, NULL);  in xgpu_ai_mailbox_flr_work()
351 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,  in xgpu_ai_set_mailbox_rcv_irq()  argument
365 static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,  in xgpu_ai_mailbox_rcv_irq()  argument
369 	enum idh_event event = xgpu_ai_mailbox_peek_msg(adev);  in xgpu_ai_mailbox_rcv_irq()
373 		if (amdgpu_sriov_runtime(adev))  in xgpu_ai_mailbox_rcv_irq()
374 			schedule_work(&adev->virt.flr_work);  in xgpu_ai_mailbox_rcv_irq()
377 			xgpu_ai_mailbox_send_ack(adev);  in xgpu_ai_mailbox_rcv_irq()
403 void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev)  in xgpu_ai_mailbox_set_irq_funcs()  argument
405 	adev->virt.ack_irq.num_types = 1;  in xgpu_ai_mailbox_set_irq_funcs()
406 	adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;  in xgpu_ai_mailbox_set_irq_funcs()
407 	adev->virt.rcv_irq.num_types = 1;  in xgpu_ai_mailbox_set_irq_funcs()
408 	adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs;  in xgpu_ai_mailbox_set_irq_funcs()
411 int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)  in xgpu_ai_mailbox_add_irq_id()  argument
415 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);  in xgpu_ai_mailbox_add_irq_id()
419 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);  in xgpu_ai_mailbox_add_irq_id()
421 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_add_irq_id()
428 int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev)  in xgpu_ai_mailbox_get_irq()  argument
432 	r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_get_irq()
435 	r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);  in xgpu_ai_mailbox_get_irq()
437 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_get_irq()
441 	INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work);  in xgpu_ai_mailbox_get_irq()
446 void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)  in xgpu_ai_mailbox_put_irq()  argument
448 	amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);  in xgpu_ai_mailbox_put_irq()
449 	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_put_irq()