Lines Matching refs:adev
90 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
94 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
95 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
97 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
101 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
105 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
109 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
110 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
112 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
117 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
120 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg64() argument
124 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg64()
125 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg64()
127 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg64()
137 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg64()
141 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in soc15_pcie_wreg64() argument
145 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg64()
146 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg64()
148 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg64()
160 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg64()
163 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in soc15_uvd_ctx_rreg() argument
171 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
174 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
178 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_uvd_ctx_wreg() argument
185 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
188 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
191 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc15_didt_rreg() argument
199 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
202 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
206 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_didt_wreg() argument
213 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
216 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
219 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_gc_cac_rreg() argument
224 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
227 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
231 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_gc_cac_wreg() argument
235 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
238 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
241 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_se_cac_rreg() argument
246 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
249 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
253 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_se_cac_wreg() argument
257 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
260 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
263 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) in soc15_get_config_memsize() argument
265 return adev->nbio_funcs->get_memsize(adev); in soc15_get_config_memsize()
268 static u32 soc15_get_xclk(struct amdgpu_device *adev) in soc15_get_xclk() argument
270 return adev->clock.spll.reference_freq; in soc15_get_xclk()
274 void soc15_grbm_select(struct amdgpu_device *adev, in soc15_grbm_select() argument
286 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) in soc15_vga_set_state() argument
291 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) in soc15_read_disabled_bios() argument
297 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, in soc15_read_bios_from_rom() argument
308 if (adev->flags & AMD_IS_APU) in soc15_read_bios_from_rom()
345 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
350 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
352 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
357 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in soc15_read_indexed_register()
358 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
362 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, in soc15_get_register_value() argument
367 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
370 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
372 return adev->gfx.config.db_debug2; in soc15_get_register_value()
377 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
386 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
390 *value = soc15_get_register_value(adev, in soc15_read_register()
410 void soc15_program_register_sequence(struct amdgpu_device *adev, in soc15_program_register_sequence() argument
420 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
442 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) in soc15_asic_mode1_reset() argument
447 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in soc15_asic_mode1_reset()
449 dev_info(adev->dev, "GPU mode1 reset\n"); in soc15_asic_mode1_reset()
452 pci_clear_master(adev->pdev); in soc15_asic_mode1_reset()
454 pci_save_state(adev->pdev); in soc15_asic_mode1_reset()
456 ret = psp_gpu_reset(adev); in soc15_asic_mode1_reset()
458 dev_err(adev->dev, "GPU mode1 reset failed\n"); in soc15_asic_mode1_reset()
460 pci_restore_state(adev->pdev); in soc15_asic_mode1_reset()
463 for (i = 0; i < adev->usec_timeout; i++) { in soc15_asic_mode1_reset()
464 u32 memsize = adev->nbio_funcs->get_memsize(adev); in soc15_asic_mode1_reset()
471 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in soc15_asic_mode1_reset()
476 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap) in soc15_asic_get_baco_capability() argument
478 void *pp_handle = adev->powerplay.pp_handle; in soc15_asic_get_baco_capability()
479 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in soc15_asic_get_baco_capability()
489 static int soc15_asic_baco_reset(struct amdgpu_device *adev) in soc15_asic_baco_reset() argument
491 void *pp_handle = adev->powerplay.pp_handle; in soc15_asic_baco_reset()
492 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in soc15_asic_baco_reset()
505 dev_info(adev->dev, "GPU BACO reset\n"); in soc15_asic_baco_reset()
507 adev->in_baco_reset = 1; in soc15_asic_baco_reset()
512 static int soc15_mode2_reset(struct amdgpu_device *adev) in soc15_mode2_reset() argument
514 if (!adev->powerplay.pp_funcs || in soc15_mode2_reset()
515 !adev->powerplay.pp_funcs->asic_reset_mode_2) in soc15_mode2_reset()
518 return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle); in soc15_mode2_reset()
522 soc15_asic_reset_method(struct amdgpu_device *adev) in soc15_asic_reset_method() argument
526 switch (adev->asic_type) { in soc15_asic_reset_method()
531 soc15_asic_get_baco_capability(adev, &baco_reset); in soc15_asic_reset_method()
534 if (adev->psp.sos_fw_version >= 0x80067) in soc15_asic_reset_method()
535 soc15_asic_get_baco_capability(adev, &baco_reset); in soc15_asic_reset_method()
539 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0); in soc15_asic_reset_method()
540 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method()
557 static int soc15_asic_reset(struct amdgpu_device *adev) in soc15_asic_reset() argument
559 switch (soc15_asic_reset_method(adev)) { in soc15_asic_reset()
561 if (!adev->in_suspend) in soc15_asic_reset()
562 amdgpu_inc_vram_lost(adev); in soc15_asic_reset()
563 return soc15_asic_baco_reset(adev); in soc15_asic_reset()
565 return soc15_mode2_reset(adev); in soc15_asic_reset()
567 if (!adev->in_suspend) in soc15_asic_reset()
568 amdgpu_inc_vram_lost(adev); in soc15_asic_reset()
569 return soc15_asic_mode1_reset(adev); in soc15_asic_reset()
579 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc15_set_uvd_clocks() argument
592 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
599 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) in soc15_pcie_gen3_enable() argument
601 if (pci_is_root_bus(adev->pdev->bus)) in soc15_pcie_gen3_enable()
607 if (adev->flags & AMD_IS_APU) in soc15_pcie_gen3_enable()
610 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in soc15_pcie_gen3_enable()
617 static void soc15_program_aspm(struct amdgpu_device *adev) in soc15_program_aspm() argument
626 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, in soc15_enable_doorbell_aperture() argument
629 adev->nbio_funcs->enable_doorbell_aperture(adev, enable); in soc15_enable_doorbell_aperture()
630 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); in soc15_enable_doorbell_aperture()
642 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) in soc15_get_rev_id() argument
644 return adev->nbio_funcs->get_rev_id(adev); in soc15_get_rev_id()
647 int soc15_set_ip_blocks(struct amdgpu_device *adev) in soc15_set_ip_blocks() argument
650 switch (adev->asic_type) { in soc15_set_ip_blocks()
655 vega10_reg_base_init(adev); in soc15_set_ip_blocks()
658 vega20_reg_base_init(adev); in soc15_set_ip_blocks()
661 arct_reg_base_init(adev); in soc15_set_ip_blocks()
667 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) in soc15_set_ip_blocks()
668 adev->gmc.xgmi.supported = true; in soc15_set_ip_blocks()
670 if (adev->flags & AMD_IS_APU) in soc15_set_ip_blocks()
671 adev->nbio_funcs = &nbio_v7_0_funcs; in soc15_set_ip_blocks()
672 else if (adev->asic_type == CHIP_VEGA20 || in soc15_set_ip_blocks()
673 adev->asic_type == CHIP_ARCTURUS) in soc15_set_ip_blocks()
674 adev->nbio_funcs = &nbio_v7_4_funcs; in soc15_set_ip_blocks()
676 adev->nbio_funcs = &nbio_v6_1_funcs; in soc15_set_ip_blocks()
678 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) in soc15_set_ip_blocks()
679 adev->df_funcs = &df_v3_6_funcs; in soc15_set_ip_blocks()
681 adev->df_funcs = &df_v1_7_funcs; in soc15_set_ip_blocks()
683 adev->rev_id = soc15_get_rev_id(adev); in soc15_set_ip_blocks()
684 adev->nbio_funcs->detect_hw_virt(adev); in soc15_set_ip_blocks()
686 if (amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
687 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_ip_blocks()
689 switch (adev->asic_type) { in soc15_set_ip_blocks()
693 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
694 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
697 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
698 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { in soc15_set_ip_blocks()
699 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
700 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
702 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); in soc15_set_ip_blocks()
704 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
706 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
707 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { in soc15_set_ip_blocks()
708 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
709 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
711 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); in soc15_set_ip_blocks()
714 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
715 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
716 if (!amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
717 if (is_support_sw_smu(adev)) in soc15_set_ip_blocks()
718 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in soc15_set_ip_blocks()
720 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in soc15_set_ip_blocks()
722 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
723 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
725 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
726 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
728 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { in soc15_set_ip_blocks()
729 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); in soc15_set_ip_blocks()
730 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); in soc15_set_ip_blocks()
734 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
735 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
736 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
737 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
738 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); in soc15_set_ip_blocks()
739 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
740 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
741 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in soc15_set_ip_blocks()
742 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
743 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
745 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
746 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
748 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); in soc15_set_ip_blocks()
751 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
752 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
753 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
754 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
755 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
756 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
757 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
758 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in soc15_set_ip_blocks()
759 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); in soc15_set_ip_blocks()
762 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
763 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
764 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
765 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
766 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); in soc15_set_ip_blocks()
767 if (is_support_sw_smu(adev)) in soc15_set_ip_blocks()
768 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); in soc15_set_ip_blocks()
769 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
770 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
771 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
772 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
774 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
775 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
777 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in soc15_set_ip_blocks()
786 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in soc15_flush_hdp() argument
788 adev->nbio_funcs->hdp_flush(adev, ring); in soc15_flush_hdp()
791 static void soc15_invalidate_hdp(struct amdgpu_device *adev, in soc15_invalidate_hdp() argument
801 static bool soc15_need_full_reset(struct amdgpu_device *adev) in soc15_need_full_reset() argument
806 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in soc15_get_pcie_usage() argument
816 if (adev->flags & AMD_IS_APU) in soc15_get_pcie_usage()
853 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vega20_get_pcie_usage() argument
863 if (adev->flags & AMD_IS_APU) in vega20_get_pcie_usage()
902 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) in soc15_need_reset_on_init() argument
909 if (!amdgpu_passthrough(adev)) in soc15_need_reset_on_init()
912 if (adev->flags & AMD_IS_APU) in soc15_need_reset_on_init()
925 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) in soc15_get_pcie_replay_count() argument
982 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_early_init() local
984 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in soc15_common_early_init()
985 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in soc15_common_early_init()
986 adev->smc_rreg = NULL; in soc15_common_early_init()
987 adev->smc_wreg = NULL; in soc15_common_early_init()
988 adev->pcie_rreg = &soc15_pcie_rreg; in soc15_common_early_init()
989 adev->pcie_wreg = &soc15_pcie_wreg; in soc15_common_early_init()
990 adev->pcie_rreg64 = &soc15_pcie_rreg64; in soc15_common_early_init()
991 adev->pcie_wreg64 = &soc15_pcie_wreg64; in soc15_common_early_init()
992 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
993 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
994 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
995 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
996 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
997 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
998 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
999 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
1002 adev->external_rev_id = 0xFF; in soc15_common_early_init()
1003 switch (adev->asic_type) { in soc15_common_early_init()
1005 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1006 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1025 adev->pg_flags = 0; in soc15_common_early_init()
1026 adev->external_rev_id = 0x1; in soc15_common_early_init()
1029 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1030 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1048 adev->pg_flags = 0; in soc15_common_early_init()
1049 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1052 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1053 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1071 adev->pg_flags = 0; in soc15_common_early_init()
1072 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1075 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1076 if (adev->rev_id >= 0x8) in soc15_common_early_init()
1077 adev->external_rev_id = adev->rev_id + 0x79; in soc15_common_early_init()
1078 else if (adev->pdev->device == 0x15d8) in soc15_common_early_init()
1079 adev->external_rev_id = adev->rev_id + 0x41; in soc15_common_early_init()
1080 else if (adev->rev_id == 1) in soc15_common_early_init()
1081 adev->external_rev_id = adev->rev_id + 0x20; in soc15_common_early_init()
1083 adev->external_rev_id = adev->rev_id + 0x01; in soc15_common_early_init()
1085 if (adev->rev_id >= 0x8) { in soc15_common_early_init()
1086 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1102 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1103 } else if (adev->pdev->device == 0x15d8) { in soc15_common_early_init()
1104 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1119 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1124 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1145 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1149 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1150 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1161 adev->pg_flags = 0; in soc15_common_early_init()
1162 adev->external_rev_id = adev->rev_id + 0x32; in soc15_common_early_init()
1165 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1166 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1185 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1188 adev->external_rev_id = adev->rev_id + 0x91; in soc15_common_early_init()
1195 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1196 amdgpu_virt_init_setting(adev); in soc15_common_early_init()
1197 xgpu_ai_mailbox_set_irq_funcs(adev); in soc15_common_early_init()
1205 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_late_init() local
1207 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1208 xgpu_ai_mailbox_get_irq(adev); in soc15_common_late_init()
1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_init() local
1217 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1218 xgpu_ai_mailbox_add_irq_id(adev); in soc15_common_sw_init()
1220 adev->df_funcs->sw_init(adev); in soc15_common_sw_init()
1230 static void soc15_doorbell_range_init(struct amdgpu_device *adev) in soc15_doorbell_range_init() argument
1236 if (!amdgpu_sriov_vf(adev)) { in soc15_doorbell_range_init()
1237 for (i = 0; i < adev->sdma.num_instances; i++) { in soc15_doorbell_range_init()
1238 ring = &adev->sdma.instance[i].ring; in soc15_doorbell_range_init()
1239 adev->nbio_funcs->sdma_doorbell_range(adev, i, in soc15_doorbell_range_init()
1241 adev->doorbell_index.sdma_doorbell_range); in soc15_doorbell_range_init()
1244 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in soc15_doorbell_range_init()
1245 adev->irq.ih.doorbell_index); in soc15_doorbell_range_init()
1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_init() local
1254 soc15_pcie_gen3_enable(adev); in soc15_common_hw_init()
1256 soc15_program_aspm(adev); in soc15_common_hw_init()
1258 adev->nbio_funcs->init_registers(adev); in soc15_common_hw_init()
1263 if (adev->nbio_funcs->remap_hdp_registers) in soc15_common_hw_init()
1264 adev->nbio_funcs->remap_hdp_registers(adev); in soc15_common_hw_init()
1267 soc15_enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
1273 soc15_doorbell_range_init(adev); in soc15_common_hw_init()
1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_fini() local
1283 soc15_enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
1284 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1285 xgpu_ai_mailbox_put_irq(adev); in soc15_common_hw_fini()
1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_suspend() local
1294 return soc15_common_hw_fini(adev); in soc15_common_suspend()
1299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_resume() local
1301 return soc15_common_hw_init(adev); in soc15_common_resume()
1319 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_hdp_light_sleep() argument
1323 if (adev->asic_type == CHIP_VEGA20 || in soc15_update_hdp_light_sleep()
1324 adev->asic_type == CHIP_ARCTURUS) { in soc15_update_hdp_light_sleep()
1327 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in soc15_update_hdp_light_sleep()
1343 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in soc15_update_hdp_light_sleep()
1353 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) in soc15_update_drm_clock_gating() argument
1359 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
1382 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_drm_light_sleep() argument
1388 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
1397 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, in soc15_update_rom_medium_grain_clock_gating() argument
1404 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) in soc15_update_rom_medium_grain_clock_gating()
1418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_set_clockgating_state() local
1420 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1423 switch (adev->asic_type) { in soc15_common_set_clockgating_state()
1427 adev->nbio_funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1429 adev->nbio_funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1431 soc15_update_hdp_light_sleep(adev, in soc15_common_set_clockgating_state()
1433 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1435 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1437 soc15_update_rom_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1439 adev->df_funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1444 adev->nbio_funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1446 adev->nbio_funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1448 soc15_update_hdp_light_sleep(adev, in soc15_common_set_clockgating_state()
1450 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1452 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1454 soc15_update_rom_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1458 soc15_update_hdp_light_sleep(adev, in soc15_common_set_clockgating_state()
1469 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_get_clockgating_state() local
1472 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
1475 adev->nbio_funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
1497 adev->df_funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()