Lines Matching refs:adev
62 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
66 address = adev->nbio_funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
67 data = adev->nbio_funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
69 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in nv_pcie_rreg()
73 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in nv_pcie_rreg()
77 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
81 address = adev->nbio_funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
82 data = adev->nbio_funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
84 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in nv_pcie_wreg()
89 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in nv_pcie_wreg()
92 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) in nv_didt_rreg() argument
100 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg()
103 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_rreg()
107 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_didt_wreg() argument
114 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_wreg()
117 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_wreg()
120 static u32 nv_get_config_memsize(struct amdgpu_device *adev) in nv_get_config_memsize() argument
122 return adev->nbio_funcs->get_memsize(adev); in nv_get_config_memsize()
125 static u32 nv_get_xclk(struct amdgpu_device *adev) in nv_get_xclk() argument
127 return adev->clock.spll.reference_freq; in nv_get_xclk()
131 void nv_grbm_select(struct amdgpu_device *adev, in nv_grbm_select() argument
143 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) in nv_vga_set_state() argument
148 static bool nv_read_disabled_bios(struct amdgpu_device *adev) in nv_read_disabled_bios() argument
154 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, in nv_read_bios_from_rom() argument
184 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
189 mutex_lock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
191 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
196 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in nv_read_indexed_register()
197 mutex_unlock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
201 static uint32_t nv_get_register_value(struct amdgpu_device *adev, in nv_get_register_value() argument
206 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
209 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
214 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
224 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) in nv_read_register()
227 *value = nv_get_register_value(adev, in nv_read_register()
236 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev)
240 dev_info(adev->dev, "GPU pci config reset\n");
243 pci_clear_master(adev->pdev);
245 amdgpu_pci_config_reset(adev);
250 for (i = 0; i < adev->usec_timeout; i++) {
251 u32 memsize = nbio_v2_3_get_memsize(adev);
260 static int nv_asic_mode1_reset(struct amdgpu_device *adev) in nv_asic_mode1_reset() argument
265 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_mode1_reset()
267 dev_info(adev->dev, "GPU mode1 reset\n"); in nv_asic_mode1_reset()
270 pci_clear_master(adev->pdev); in nv_asic_mode1_reset()
272 pci_save_state(adev->pdev); in nv_asic_mode1_reset()
274 ret = psp_gpu_reset(adev); in nv_asic_mode1_reset()
276 dev_err(adev->dev, "GPU mode1 reset failed\n"); in nv_asic_mode1_reset()
278 pci_restore_state(adev->pdev); in nv_asic_mode1_reset()
281 for (i = 0; i < adev->usec_timeout; i++) { in nv_asic_mode1_reset()
282 u32 memsize = adev->nbio_funcs->get_memsize(adev); in nv_asic_mode1_reset()
289 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_mode1_reset()
295 nv_asic_reset_method(struct amdgpu_device *adev) in nv_asic_reset_method() argument
297 struct smu_context *smu = &adev->smu; in nv_asic_reset_method()
305 static int nv_asic_reset(struct amdgpu_device *adev) in nv_asic_reset() argument
310 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_reset()
312 nv_gpu_pci_config_reset(adev); in nv_asic_reset()
314 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_reset()
317 struct smu_context *smu = &adev->smu; in nv_asic_reset()
319 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { in nv_asic_reset()
320 if (!adev->in_suspend) in nv_asic_reset()
321 amdgpu_inc_vram_lost(adev); in nv_asic_reset()
324 if (!adev->in_suspend) in nv_asic_reset()
325 amdgpu_inc_vram_lost(adev); in nv_asic_reset()
326 ret = nv_asic_mode1_reset(adev); in nv_asic_reset()
332 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in nv_set_uvd_clocks() argument
338 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
344 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) in nv_pcie_gen3_enable() argument
346 if (pci_is_root_bus(adev->pdev->bus)) in nv_pcie_gen3_enable()
352 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in nv_pcie_gen3_enable()
359 static void nv_program_aspm(struct amdgpu_device *adev) in nv_program_aspm() argument
368 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, in nv_enable_doorbell_aperture() argument
371 adev->nbio_funcs->enable_doorbell_aperture(adev, enable); in nv_enable_doorbell_aperture()
372 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); in nv_enable_doorbell_aperture()
384 static int nv_reg_base_init(struct amdgpu_device *adev) in nv_reg_base_init() argument
389 r = amdgpu_discovery_reg_base_init(adev); in nv_reg_base_init()
400 switch (adev->asic_type) { in nv_reg_base_init()
402 navi10_reg_base_init(adev); in nv_reg_base_init()
405 navi14_reg_base_init(adev); in nv_reg_base_init()
408 navi12_reg_base_init(adev); in nv_reg_base_init()
417 int nv_set_ip_blocks(struct amdgpu_device *adev) in nv_set_ip_blocks() argument
422 r = nv_reg_base_init(adev); in nv_set_ip_blocks()
426 adev->nbio_funcs = &nbio_v2_3_funcs; in nv_set_ip_blocks()
428 adev->nbio_funcs->detect_hw_virt(adev); in nv_set_ip_blocks()
430 switch (adev->asic_type) { in nv_set_ip_blocks()
433 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
434 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
435 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
436 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
437 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
438 is_support_sw_smu(adev)) in nv_set_ip_blocks()
439 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
440 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
441 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in nv_set_ip_blocks()
443 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
444 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
446 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
447 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
448 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
449 is_support_sw_smu(adev)) in nv_set_ip_blocks()
450 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
451 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in nv_set_ip_blocks()
452 if (adev->enable_mes) in nv_set_ip_blocks()
453 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); in nv_set_ip_blocks()
456 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
457 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
458 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
459 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
460 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
461 is_support_sw_smu(adev)) in nv_set_ip_blocks()
462 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
463 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
464 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in nv_set_ip_blocks()
466 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
467 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
469 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
470 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
471 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
472 is_support_sw_smu(adev)) in nv_set_ip_blocks()
473 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
474 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in nv_set_ip_blocks()
483 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) in nv_get_rev_id() argument
485 return adev->nbio_funcs->get_rev_id(adev); in nv_get_rev_id()
488 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in nv_flush_hdp() argument
490 adev->nbio_funcs->hdp_flush(adev, ring); in nv_flush_hdp()
493 static void nv_invalidate_hdp(struct amdgpu_device *adev, in nv_invalidate_hdp() argument
504 static bool nv_need_full_reset(struct amdgpu_device *adev) in nv_need_full_reset() argument
509 static void nv_get_pcie_usage(struct amdgpu_device *adev, in nv_get_pcie_usage() argument
516 static bool nv_need_reset_on_init(struct amdgpu_device *adev) in nv_need_reset_on_init() argument
521 if (adev->flags & AMD_IS_APU) in nv_need_reset_on_init()
535 static void nv_init_doorbell_index(struct amdgpu_device *adev) in nv_init_doorbell_index() argument
537 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
538 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in nv_init_doorbell_index()
539 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in nv_init_doorbell_index()
540 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in nv_init_doorbell_index()
541 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in nv_init_doorbell_index()
542 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in nv_init_doorbell_index()
543 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in nv_init_doorbell_index()
544 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in nv_init_doorbell_index()
545 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in nv_init_doorbell_index()
546 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in nv_init_doorbell_index()
547 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in nv_init_doorbell_index()
548 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in nv_init_doorbell_index()
549 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in nv_init_doorbell_index()
550 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in nv_init_doorbell_index()
551 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in nv_init_doorbell_index()
552 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in nv_init_doorbell_index()
553 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
554 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
555 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
556 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
557 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in nv_init_doorbell_index()
558 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in nv_init_doorbell_index()
560 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in nv_init_doorbell_index()
561 adev->doorbell_index.sdma_doorbell_range = 20; in nv_init_doorbell_index()
586 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_early_init() local
588 adev->smc_rreg = NULL; in nv_common_early_init()
589 adev->smc_wreg = NULL; in nv_common_early_init()
590 adev->pcie_rreg = &nv_pcie_rreg; in nv_common_early_init()
591 adev->pcie_wreg = &nv_pcie_wreg; in nv_common_early_init()
594 adev->uvd_ctx_rreg = NULL; in nv_common_early_init()
595 adev->uvd_ctx_wreg = NULL; in nv_common_early_init()
597 adev->didt_rreg = &nv_didt_rreg; in nv_common_early_init()
598 adev->didt_wreg = &nv_didt_wreg; in nv_common_early_init()
600 adev->asic_funcs = &nv_asic_funcs; in nv_common_early_init()
602 adev->rev_id = nv_get_rev_id(adev); in nv_common_early_init()
603 adev->external_rev_id = 0xff; in nv_common_early_init()
604 switch (adev->asic_type) { in nv_common_early_init()
606 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
620 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
623 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
626 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
640 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
642 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
645 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
660 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
663 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
690 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_init() local
693 nv_pcie_gen3_enable(adev); in nv_common_hw_init()
695 nv_program_aspm(adev); in nv_common_hw_init()
697 adev->nbio_funcs->init_registers(adev); in nv_common_hw_init()
699 nv_enable_doorbell_aperture(adev, true); in nv_common_hw_init()
706 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_fini() local
709 nv_enable_doorbell_aperture(adev, false); in nv_common_hw_fini()
716 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_suspend() local
718 return nv_common_hw_fini(adev); in nv_common_suspend()
723 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_resume() local
725 return nv_common_hw_init(adev); in nv_common_resume()
743 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, in nv_update_hdp_mem_power_gating() argument
749 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | in nv_update_hdp_mem_power_gating()
786 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { in nv_update_hdp_mem_power_gating()
793 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { in nv_update_hdp_mem_power_gating()
800 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { in nv_update_hdp_mem_power_gating()
816 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, in nv_update_hdp_clock_gating() argument
821 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) in nv_update_hdp_clock_gating()
850 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_set_clockgating_state() local
852 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
855 switch (adev->asic_type) { in nv_common_set_clockgating_state()
859 adev->nbio_funcs->update_medium_grain_clock_gating(adev, in nv_common_set_clockgating_state()
861 adev->nbio_funcs->update_medium_grain_light_sleep(adev, in nv_common_set_clockgating_state()
863 nv_update_hdp_mem_power_gating(adev, in nv_common_set_clockgating_state()
865 nv_update_hdp_clock_gating(adev, in nv_common_set_clockgating_state()
883 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_get_clockgating_state() local
886 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
889 adev->nbio_funcs->get_clockgating_state(adev, flags); in nv_common_get_clockgating_state()