96 	struct amdgpu_device		*adev;  member
261 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
263 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
265 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
291 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
296 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
299 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
305 bool amdgpu_get_bios(struct amdgpu_device *adev);
306 bool amdgpu_read_bios(struct amdgpu_device *adev);
386 	struct amdgpu_device		*adev;  member
428 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
430 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
432 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
437 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
438 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
439 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
457 	struct amdgpu_device	*adev;  member
515 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
516 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
521 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
527 void amdgpu_test_moves(struct amdgpu_device *adev);
549 	bool (*read_disabled_bios)(struct amdgpu_device *adev);
550 	bool (*read_bios_from_rom)(struct amdgpu_device *adev,
552 	int (*read_register)(struct amdgpu_device *adev, u32 se_num,
554 	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
555 	int (*reset)(struct amdgpu_device *adev);
556 	enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
558 	u32 (*get_xclk)(struct amdgpu_device *adev);
560 	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
561 	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
563 	int (*get_pcie_lanes)(struct amdgpu_device *adev);
564 	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
566 	u32 (*get_config_memsize)(struct amdgpu_device *adev);
568 	void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
570 	void (*invalidate_hdp)(struct amdgpu_device *adev,
573 	bool (*need_full_reset)(struct amdgpu_device *adev);
575 	void (*init_doorbell_index)(struct amdgpu_device *adev);
577 	void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
580 	bool (*need_reset_on_init)(struct amdgpu_device *adev);
582 	uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
632 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
680 	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
681 	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
682 	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
683 	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
684 	u32 (*get_rev_id)(struct amdgpu_device *adev);
685 	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
686 	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
687 	u32 (*get_memsize)(struct amdgpu_device *adev);
688 	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
690 	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
692 	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
694 	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
696 	void (*ih_doorbell_range)(struct amdgpu_device *adev,
698 	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
700 	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
702 	void (*get_clockgating_state)(struct amdgpu_device *adev,
704 	void (*ih_control)(struct amdgpu_device *adev);
705 	void (*init_registers)(struct amdgpu_device *adev);
706 	void (*detect_hw_virt)(struct amdgpu_device *adev);
707 	void (*remap_hdp_registers)(struct amdgpu_device *adev);
711 	void (*sw_init)(struct amdgpu_device *adev);
712 	void (*enable_broadcast_mode)(struct amdgpu_device *adev,
714 	u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
715 	u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
716 	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
718 	void (*get_clockgating_state)(struct amdgpu_device *adev,
720 	void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
722 	int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
724 	int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
726 	void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
728 	uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
729 	void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
1028 int amdgpu_device_init(struct amdgpu_device *adev,
1032 void amdgpu_device_fini(struct amdgpu_device *adev);
1033 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1035 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1037 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1039 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1040 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1042 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1043 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1046 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1048 int emu_soc_asic_init(struct amdgpu_device *adev);
1057 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1058 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1060 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1061 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1063 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1064 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1065 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0…
1066 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1067 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1070 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1071 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1072 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1073 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1074 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1075 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1076 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1077 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1078 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1079 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1080 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1081 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1082 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1083 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1084 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1085 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1086 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1087 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1104 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (re…  argument
1105 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1106 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1127 #define RBIOS8(i) (adev->bios[i])
1134 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))  argument
1135 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))  argument
1136 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))  argument
1137 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))  argument
1138 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))  argument
1139 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (…  argument
1140 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))  argument
1141 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))  argument
1142 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))  argument
1143 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))  argument
1144 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (…  argument
1145 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev)…  argument
1146 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))  argument
1147 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))  argument
1148 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))  argument
1149 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))  argument
1150 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))  argument
1151 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (c…  argument
1152 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))  argument
1153 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))  argument
1154 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));  argument
1157 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1158 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1160 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1161 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1163 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1165 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1166 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1171 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1209 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1239 int amdgpu_acpi_init(struct amdgpu_device *adev);
1240 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1241 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1242 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1244 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1246 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1249 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }  in amdgpu_acpi_init()  argument
1250 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }  in amdgpu_acpi_fini()  argument
1258 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1260 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }  in amdgpu_dm_display_resume()  argument
1264 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1265 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);