Lines Matching refs:adev
58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v10_0_vm_fault_interrupt_state() argument
84 hub = &adev->vmhub[AMDGPU_MMHUB_0]; in gmc_v10_0_vm_fault_interrupt_state()
93 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; in gmc_v10_0_vm_fault_interrupt_state()
103 hub = &adev->vmhub[AMDGPU_MMHUB_0]; in gmc_v10_0_vm_fault_interrupt_state()
112 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; in gmc_v10_0_vm_fault_interrupt_state()
127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, in gmc_v10_0_process_interrupt() argument
131 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v10_0_process_interrupt()
138 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
155 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); in gmc_v10_0_process_interrupt()
157 dev_err(adev->dev, in gmc_v10_0_process_interrupt()
164 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", in gmc_v10_0_process_interrupt()
166 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
167 dev_err(adev->dev, in gmc_v10_0_process_interrupt()
170 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", in gmc_v10_0_process_interrupt()
173 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", in gmc_v10_0_process_interrupt()
176 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", in gmc_v10_0_process_interrupt()
179 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", in gmc_v10_0_process_interrupt()
182 dev_err(adev->dev, "\t RW: 0x%lx\n", in gmc_v10_0_process_interrupt()
196 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) in gmc_v10_0_set_irq_funcs() argument
198 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
199 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
229 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, in gmc_v10_0_flush_vm_hub() argument
232 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; in gmc_v10_0_flush_vm_hub()
248 for (i = 0; i < adev->usec_timeout; i++) { in gmc_v10_0_flush_vm_hub()
257 if (i < adev->usec_timeout) in gmc_v10_0_flush_vm_hub()
271 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v10_0_flush_gpu_tlb() argument
274 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; in gmc_v10_0_flush_gpu_tlb()
281 adev->nbio_funcs->hdp_flush(adev, NULL); in gmc_v10_0_flush_gpu_tlb()
283 mutex_lock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
286 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); in gmc_v10_0_flush_gpu_tlb()
287 mutex_unlock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
293 if (!adev->mman.buffer_funcs_enabled || in gmc_v10_0_flush_gpu_tlb()
294 !adev->ib_pool_ready || in gmc_v10_0_flush_gpu_tlb()
295 adev->in_gpu_reset) { in gmc_v10_0_flush_gpu_tlb()
296 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); in gmc_v10_0_flush_gpu_tlb()
297 mutex_unlock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
306 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job); in gmc_v10_0_flush_gpu_tlb()
310 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); in gmc_v10_0_flush_gpu_tlb()
314 r = amdgpu_job_submit(job, &adev->mman.entity, in gmc_v10_0_flush_gpu_tlb()
319 mutex_unlock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
330 mutex_unlock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
337 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in gmc_v10_0_emit_flush_gpu_tlb()
357 struct amdgpu_device *adev = ring->adev; in gmc_v10_0_emit_pasid_mapping() local
399 static uint64_t gmc_v10_0_get_vm_pte_flags(struct amdgpu_device *adev, in gmc_v10_0_get_vm_pte_flags() argument
438 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, in gmc_v10_0_get_vm_pde() argument
442 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v10_0_get_vm_pde()
443 adev->gmc.vram_start; in gmc_v10_0_get_vm_pde()
446 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
470 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) in gmc_v10_0_set_gmc_funcs() argument
472 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
473 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_early_init() local
480 gmc_v10_0_set_gmc_funcs(adev); in gmc_v10_0_early_init()
481 gmc_v10_0_set_irq_funcs(adev); in gmc_v10_0_early_init()
483 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v10_0_early_init()
484 adev->gmc.shared_aperture_end = in gmc_v10_0_early_init()
485 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v10_0_early_init()
486 adev->gmc.private_aperture_start = 0x1000000000000000ULL; in gmc_v10_0_early_init()
487 adev->gmc.private_aperture_end = in gmc_v10_0_early_init()
488 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v10_0_early_init()
495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_late_init() local
499 for(i = 0; i < adev->num_rings; ++i) { in gmc_v10_0_late_init()
500 struct amdgpu_ring *ring = adev->rings[i]; in gmc_v10_0_late_init()
504 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n", in gmc_v10_0_late_init()
513 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_late_init()
516 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, in gmc_v10_0_vram_gtt_location() argument
521 if (!amdgpu_sriov_vf(adev)) in gmc_v10_0_vram_gtt_location()
522 base = gfxhub_v2_0_get_fb_location(adev); in gmc_v10_0_vram_gtt_location()
524 amdgpu_gmc_vram_location(adev, &adev->gmc, base); in gmc_v10_0_vram_gtt_location()
525 amdgpu_gmc_gart_location(adev, mc); in gmc_v10_0_vram_gtt_location()
528 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); in gmc_v10_0_vram_gtt_location()
540 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) in gmc_v10_0_mc_init() argument
545 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); in gmc_v10_0_mc_init()
550 adev->gmc.vram_width = numchan * chansize; in gmc_v10_0_mc_init()
554 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v10_0_mc_init()
555 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v10_0_mc_init()
558 adev->gmc.mc_vram_size = in gmc_v10_0_mc_init()
559 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v10_0_mc_init()
560 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v10_0_mc_init()
561 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v10_0_mc_init()
564 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) in gmc_v10_0_mc_init()
565 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; in gmc_v10_0_mc_init()
569 switch (adev->asic_type) { in gmc_v10_0_mc_init()
574 adev->gmc.gart_size = 512ULL << 20; in gmc_v10_0_mc_init()
578 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v10_0_mc_init()
580 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); in gmc_v10_0_mc_init()
585 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) in gmc_v10_0_gart_init() argument
589 if (adev->gart.bo) { in gmc_v10_0_gart_init()
595 r = amdgpu_gart_init(adev); in gmc_v10_0_gart_init()
599 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v10_0_gart_init()
600 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | in gmc_v10_0_gart_init()
603 return amdgpu_gart_table_vram_alloc(adev); in gmc_v10_0_gart_init()
606 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) in gmc_v10_0_get_vbios_fb_size() argument
625 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) { in gmc_v10_0_get_vbios_fb_size()
639 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_sw_init() local
641 gfxhub_v2_0_init(adev); in gmc_v10_0_sw_init()
642 mmhub_v2_0_init(adev); in gmc_v10_0_sw_init()
644 spin_lock_init(&adev->gmc.invalidate_lock); in gmc_v10_0_sw_init()
646 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); in gmc_v10_0_sw_init()
647 switch (adev->asic_type) { in gmc_v10_0_sw_init()
651 adev->num_vmhubs = 2; in gmc_v10_0_sw_init()
657 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); in gmc_v10_0_sw_init()
664 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, in gmc_v10_0_sw_init()
666 &adev->gmc.vm_fault); in gmc_v10_0_sw_init()
667 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, in gmc_v10_0_sw_init()
669 &adev->gmc.vm_fault); in gmc_v10_0_sw_init()
677 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ in gmc_v10_0_sw_init()
684 adev->gmc.stolen_size = 0; in gmc_v10_0_sw_init()
686 adev->gmc.stolen_size = 9 * 1024 *1024; in gmc_v10_0_sw_init()
688 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); in gmc_v10_0_sw_init()
694 r = gmc_v10_0_mc_init(adev); in gmc_v10_0_sw_init()
698 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev); in gmc_v10_0_sw_init()
701 r = amdgpu_bo_init(adev); in gmc_v10_0_sw_init()
705 r = gmc_v10_0_gart_init(adev); in gmc_v10_0_sw_init()
715 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v10_0_sw_init()
716 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v10_0_sw_init()
718 amdgpu_vm_manager_init(adev); in gmc_v10_0_sw_init()
730 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) in gmc_v10_0_gart_fini() argument
732 amdgpu_gart_table_vram_free(adev); in gmc_v10_0_gart_fini()
733 amdgpu_gart_fini(adev); in gmc_v10_0_gart_fini()
738 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_sw_fini() local
740 amdgpu_vm_manager_fini(adev); in gmc_v10_0_sw_fini()
741 gmc_v10_0_gart_fini(adev); in gmc_v10_0_sw_fini()
742 amdgpu_gem_force_release(adev); in gmc_v10_0_sw_fini()
743 amdgpu_bo_fini(adev); in gmc_v10_0_sw_fini()
748 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) in gmc_v10_0_init_golden_registers() argument
750 switch (adev->asic_type) { in gmc_v10_0_init_golden_registers()
765 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) in gmc_v10_0_gart_enable() argument
771 if (adev->gart.bo == NULL) { in gmc_v10_0_gart_enable()
772 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v10_0_gart_enable()
776 r = amdgpu_gart_table_vram_pin(adev); in gmc_v10_0_gart_enable()
780 r = gfxhub_v2_0_gart_enable(adev); in gmc_v10_0_gart_enable()
784 r = mmhub_v2_0_gart_enable(adev); in gmc_v10_0_gart_enable()
796 adev->nbio_funcs->hdp_flush(adev, NULL); in gmc_v10_0_gart_enable()
801 gfxhub_v2_0_set_fault_enable_default(adev, value); in gmc_v10_0_gart_enable()
802 mmhub_v2_0_set_fault_enable_default(adev, value); in gmc_v10_0_gart_enable()
803 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); in gmc_v10_0_gart_enable()
804 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); in gmc_v10_0_gart_enable()
807 (unsigned)(adev->gmc.gart_size >> 20), in gmc_v10_0_gart_enable()
808 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); in gmc_v10_0_gart_enable()
810 adev->gart.ready = true; in gmc_v10_0_gart_enable()
818 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_hw_init() local
821 gmc_v10_0_init_golden_registers(adev); in gmc_v10_0_hw_init()
823 r = gmc_v10_0_gart_enable(adev); in gmc_v10_0_hw_init()
837 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) in gmc_v10_0_gart_disable() argument
839 gfxhub_v2_0_gart_disable(adev); in gmc_v10_0_gart_disable()
840 mmhub_v2_0_gart_disable(adev); in gmc_v10_0_gart_disable()
841 amdgpu_gart_table_vram_unpin(adev); in gmc_v10_0_gart_disable()
846 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_hw_fini() local
848 if (amdgpu_sriov_vf(adev)) { in gmc_v10_0_hw_fini()
854 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_hw_fini()
855 gmc_v10_0_gart_disable(adev); in gmc_v10_0_hw_fini()
862 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_suspend() local
864 gmc_v10_0_hw_fini(adev); in gmc_v10_0_suspend()
872 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_resume() local
874 r = gmc_v10_0_hw_init(adev); in gmc_v10_0_resume()
878 amdgpu_vmid_reset_all(adev); in gmc_v10_0_resume()
904 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_set_clockgating_state() local
906 r = mmhub_v2_0_set_clockgating(adev, state); in gmc_v10_0_set_clockgating_state()
910 return athub_v2_0_set_clockgating(adev, state); in gmc_v10_0_set_clockgating_state()
915 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_get_clockgating_state() local
917 mmhub_v2_0_get_clockgating(adev, flags); in gmc_v10_0_get_clockgating_state()
919 athub_v2_0_get_clockgating(adev, flags); in gmc_v10_0_get_clockgating_state()