76 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)  in cik_pcie_rreg()  argument
81 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in cik_pcie_rreg()
85 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in cik_pcie_rreg()
89 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cik_pcie_wreg()  argument
93 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in cik_pcie_wreg()
98 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in cik_pcie_wreg()
101 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)  in cik_smc_rreg()  argument
106 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cik_smc_rreg()
109 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cik_smc_rreg()
113 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cik_smc_wreg()  argument
117 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cik_smc_wreg()
120 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cik_smc_wreg()
123 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)  in cik_uvd_ctx_rreg()  argument
128 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in cik_uvd_ctx_rreg()
131 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in cik_uvd_ctx_rreg()
135 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cik_uvd_ctx_wreg()  argument
139 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in cik_uvd_ctx_wreg()
142 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in cik_uvd_ctx_wreg()
145 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)  in cik_didt_rreg()  argument
150 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in cik_didt_rreg()
153 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in cik_didt_rreg()
157 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cik_didt_wreg()  argument
161 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in cik_didt_wreg()
164 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in cik_didt_wreg()
751 static void cik_init_golden_registers(struct amdgpu_device *adev)  in cik_init_golden_registers()  argument
754 	mutex_lock(&adev->grbm_idx_mutex);  in cik_init_golden_registers()
756 	switch (adev->asic_type) {  in cik_init_golden_registers()
758 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
761 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
764 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
767 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
772 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
775 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
778 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
781 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
786 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
789 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
792 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
795 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
800 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
803 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
806 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
809 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
814 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
817 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
820 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
823 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
830 	mutex_unlock(&adev->grbm_idx_mutex);  in cik_init_golden_registers()
841 static u32 cik_get_xclk(struct amdgpu_device *adev)  in cik_get_xclk()  argument
843 	u32 reference_clock = adev->clock.spll.reference_freq;  in cik_get_xclk()
845 	if (adev->flags & AMD_IS_APU) {  in cik_get_xclk()
868 void cik_srbm_select(struct amdgpu_device *adev,  in cik_srbm_select()  argument
879 static void cik_vga_set_state(struct amdgpu_device *adev, bool state)  in cik_vga_set_state()  argument
891 static bool cik_read_disabled_bios(struct amdgpu_device *adev)  in cik_read_disabled_bios()  argument
901 	if (adev->mode_info.num_crtc) {  in cik_read_disabled_bios()
910 	if (adev->mode_info.num_crtc) {  in cik_read_disabled_bios()
923 	r = amdgpu_read_bios(adev);  in cik_read_disabled_bios()
927 	if (adev->mode_info.num_crtc) {  in cik_read_disabled_bios()
936 static bool cik_read_bios_from_rom(struct amdgpu_device *adev,  in cik_read_bios_from_rom()  argument
948 	if (adev->flags & AMD_IS_APU)  in cik_read_bios_from_rom()
954 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cik_read_bios_from_rom()
962 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cik_read_bios_from_rom()
1027 static uint32_t cik_get_register_value(struct amdgpu_device *adev,  in cik_get_register_value()  argument
1038 			return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;  in cik_get_register_value()
1040 			return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;  in cik_get_register_value()
1042 			return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;  in cik_get_register_value()
1044 			return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;  in cik_get_register_value()
1047 		mutex_lock(&adev->grbm_idx_mutex);  in cik_get_register_value()
1049 			amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);  in cik_get_register_value()
1054 			amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);  in cik_get_register_value()
1055 		mutex_unlock(&adev->grbm_idx_mutex);  in cik_get_register_value()
1062 			return adev->gfx.config.gb_addr_config;  in cik_get_register_value()
1064 			return adev->gfx.config.mc_arb_ramcfg;  in cik_get_register_value()
1098 			return adev->gfx.config.tile_mode_array[idx];  in cik_get_register_value()
1116 			return adev->gfx.config.macrotile_mode_array[idx];  in cik_get_register_value()
1123 static int cik_read_register(struct amdgpu_device *adev, u32 se_num,  in cik_read_register()  argument
1135 		*value = cik_get_register_value(adev, indexed, se_num, sh_num,  in cik_read_register()
1148 static void kv_save_regs_for_reset(struct amdgpu_device *adev,  in kv_save_regs_for_reset()  argument
1162 static void kv_restore_regs_for_reset(struct amdgpu_device *adev,  in kv_restore_regs_for_reset()  argument
1235 static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)  in cik_gpu_pci_config_reset()  argument
1241 	dev_info(adev->dev, "GPU pci config reset\n");  in cik_gpu_pci_config_reset()
1243 	if (adev->flags & AMD_IS_APU)  in cik_gpu_pci_config_reset()
1244 		kv_save_regs_for_reset(adev, &kv_save);  in cik_gpu_pci_config_reset()
1247 	pci_clear_master(adev->pdev);  in cik_gpu_pci_config_reset()
1249 	amdgpu_device_pci_config_reset(adev);  in cik_gpu_pci_config_reset()
1254 	for (i = 0; i < adev->usec_timeout; i++) {  in cik_gpu_pci_config_reset()
1257 			pci_set_master(adev->pdev);  in cik_gpu_pci_config_reset()
1258 			adev->has_hw_reset = true;  in cik_gpu_pci_config_reset()
1266 	if (adev->flags & AMD_IS_APU)  in cik_gpu_pci_config_reset()
1267 		kv_restore_regs_for_reset(adev, &kv_save);  in cik_gpu_pci_config_reset()
1281 static int cik_asic_reset(struct amdgpu_device *adev)  in cik_asic_reset()  argument
1285 	amdgpu_atombios_scratch_regs_engine_hung(adev, true);  in cik_asic_reset()
1287 	r = cik_gpu_pci_config_reset(adev);  in cik_asic_reset()
1289 	amdgpu_atombios_scratch_regs_engine_hung(adev, false);  in cik_asic_reset()
1295 cik_asic_reset_method(struct amdgpu_device *adev)  in cik_asic_reset_method()  argument
1300 static u32 cik_get_config_memsize(struct amdgpu_device *adev)  in cik_get_config_memsize()  argument
1305 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,  in cik_set_uvd_clock()  argument
1312 	r = amdgpu_atombios_get_clock_dividers(adev,  in cik_set_uvd_clock()
1335 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)  in cik_set_uvd_clocks()  argument
1339 	r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);  in cik_set_uvd_clocks()
1343 	r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);  in cik_set_uvd_clocks()
1347 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)  in cik_set_vce_clocks()  argument
1353 	r = amdgpu_atombios_get_clock_dividers(adev,  in cik_set_vce_clocks()
1384 static void cik_pcie_gen3_enable(struct amdgpu_device *adev)  in cik_pcie_gen3_enable()  argument
1386 	struct pci_dev *root = adev->pdev->bus->self;  in cik_pcie_gen3_enable()
1392 	if (pci_is_root_bus(adev->pdev->bus))  in cik_pcie_gen3_enable()
1398 	if (adev->flags & AMD_IS_APU)  in cik_pcie_gen3_enable()
1401 	if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |  in cik_pcie_gen3_enable()
1408 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {  in cik_pcie_gen3_enable()
1414 	} else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {  in cik_pcie_gen3_enable()
1426 	gpu_pos = pci_pcie_cap(adev->pdev);  in cik_pcie_gen3_enable()
1430 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {  in cik_pcie_gen3_enable()
1438 			pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);  in cik_pcie_gen3_enable()
1444 			pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);  in cik_pcie_gen3_enable()
1468 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);  in cik_pcie_gen3_enable()
1473 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);  in cik_pcie_gen3_enable()
1476 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);  in cik_pcie_gen3_enable()
1494 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);  in cik_pcie_gen3_enable()
1497 				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);  in cik_pcie_gen3_enable()
1505 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);  in cik_pcie_gen3_enable()
1508 				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);  in cik_pcie_gen3_enable()
1523 	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);  in cik_pcie_gen3_enable()
1525 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)  in cik_pcie_gen3_enable()
1527 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)  in cik_pcie_gen3_enable()
1531 	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);  in cik_pcie_gen3_enable()
1537 	for (i = 0; i < adev->usec_timeout; i++) {  in cik_pcie_gen3_enable()
1545 static void cik_program_aspm(struct amdgpu_device *adev)  in cik_program_aspm()  argument
1554 	if (pci_is_root_bus(adev->pdev->bus))  in cik_program_aspm()
1558 	if (adev->flags & AMD_IS_APU)  in cik_program_aspm()
1633 				struct pci_dev *root = adev->pdev->bus->self;  in cik_program_aspm()
1712 static uint32_t cik_get_rev_id(struct amdgpu_device *adev)  in cik_get_rev_id()  argument
1718 static void cik_detect_hw_virtualization(struct amdgpu_device *adev)  in cik_detect_hw_virtualization()  argument
1721 		adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;  in cik_detect_hw_virtualization()
1724 static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)  in cik_flush_hdp()  argument
1734 static void cik_invalidate_hdp(struct amdgpu_device *adev,  in cik_invalidate_hdp()  argument
1745 static bool cik_need_full_reset(struct amdgpu_device *adev)  in cik_need_full_reset()  argument
1751 static void cik_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,  in cik_get_pcie_usage()  argument
1761 	if (adev->flags & AMD_IS_APU)  in cik_get_pcie_usage()
1797 static bool cik_need_reset_on_init(struct amdgpu_device *adev)  in cik_need_reset_on_init()  argument
1801 	if (adev->flags & AMD_IS_APU)  in cik_need_reset_on_init()
1814 static uint64_t cik_get_pcie_replay_count(struct amdgpu_device *adev)  in cik_get_pcie_replay_count()  argument
1849 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_common_early_init()  local
1851 	adev->smc_rreg = &cik_smc_rreg;  in cik_common_early_init()
1852 	adev->smc_wreg = &cik_smc_wreg;  in cik_common_early_init()
1853 	adev->pcie_rreg = &cik_pcie_rreg;  in cik_common_early_init()
1854 	adev->pcie_wreg = &cik_pcie_wreg;  in cik_common_early_init()
1855 	adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg;  in cik_common_early_init()
1856 	adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg;  in cik_common_early_init()
1857 	adev->didt_rreg = &cik_didt_rreg;  in cik_common_early_init()
1858 	adev->didt_wreg = &cik_didt_wreg;  in cik_common_early_init()
1860 	adev->asic_funcs = &cik_asic_funcs;  in cik_common_early_init()
1862 	adev->rev_id = cik_get_rev_id(adev);  in cik_common_early_init()
1863 	adev->external_rev_id = 0xFF;  in cik_common_early_init()
1864 	switch (adev->asic_type) {  in cik_common_early_init()
1866 		adev->cg_flags =  in cik_common_early_init()
1883 		adev->pg_flags = 0;  in cik_common_early_init()
1884 		adev->external_rev_id = adev->rev_id + 0x14;  in cik_common_early_init()
1887 		adev->cg_flags =  in cik_common_early_init()
1903 		adev->pg_flags = 0;  in cik_common_early_init()
1904 		adev->external_rev_id = 0x28;  in cik_common_early_init()
1907 		adev->cg_flags =  in cik_common_early_init()
1922 		adev->pg_flags =  in cik_common_early_init()
1934 		if (adev->pdev->device == 0x1312 ||  in cik_common_early_init()
1935 			adev->pdev->device == 0x1316 ||  in cik_common_early_init()
1936 			adev->pdev->device == 0x1317)  in cik_common_early_init()
1937 			adev->external_rev_id = 0x41;  in cik_common_early_init()
1939 			adev->external_rev_id = 0x1;  in cik_common_early_init()
1943 		adev->cg_flags =  in cik_common_early_init()
1958 		adev->pg_flags =  in cik_common_early_init()
1968 		if (adev->asic_type == CHIP_KABINI) {  in cik_common_early_init()
1969 			if (adev->rev_id == 0)  in cik_common_early_init()
1970 				adev->external_rev_id = 0x81;  in cik_common_early_init()
1971 			else if (adev->rev_id == 1)  in cik_common_early_init()
1972 				adev->external_rev_id = 0x82;  in cik_common_early_init()
1973 			else if (adev->rev_id == 2)  in cik_common_early_init()
1974 				adev->external_rev_id = 0x85;  in cik_common_early_init()
1976 			adev->external_rev_id = adev->rev_id + 0xa1;  in cik_common_early_init()
1998 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_common_hw_init()  local
2001 	cik_init_golden_registers(adev);  in cik_common_hw_init()
2003 	cik_pcie_gen3_enable(adev);  in cik_common_hw_init()
2005 	cik_program_aspm(adev);  in cik_common_hw_init()
2017 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_common_suspend()  local
2019 	return cik_common_hw_fini(adev);  in cik_common_suspend()
2024 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_common_resume()  local
2026 	return cik_common_hw_init(adev);  in cik_common_resume()
2083 int cik_set_ip_blocks(struct amdgpu_device *adev)  in cik_set_ip_blocks()  argument
2085 	cik_detect_hw_virtualization(adev);  in cik_set_ip_blocks()
2087 	switch (adev->asic_type) {  in cik_set_ip_blocks()
2089 		amdgpu_device_ip_block_add(adev, &cik_common_ip_block);  in cik_set_ip_blocks()
2090 		amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);  in cik_set_ip_blocks()
2091 		amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);  in cik_set_ip_blocks()
2092 		amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);  in cik_set_ip_blocks()
2093 		amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);  in cik_set_ip_blocks()
2094 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in cik_set_ip_blocks()
2095 		if (adev->enable_virtual_display)  in cik_set_ip_blocks()
2096 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in cik_set_ip_blocks()
2098 		else if (amdgpu_device_has_dc_support(adev))  in cik_set_ip_blocks()
2099 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in cik_set_ip_blocks()
2102 			amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);  in cik_set_ip_blocks()
2103 		amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);  in cik_set_ip_blocks()
2104 		amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);  in cik_set_ip_blocks()
2107 		amdgpu_device_ip_block_add(adev, &cik_common_ip_block);  in cik_set_ip_blocks()
2108 		amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);  in cik_set_ip_blocks()
2109 		amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);  in cik_set_ip_blocks()
2110 		amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);  in cik_set_ip_blocks()
2111 		amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);  in cik_set_ip_blocks()
2112 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in cik_set_ip_blocks()
2113 		if (adev->enable_virtual_display)  in cik_set_ip_blocks()
2114 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in cik_set_ip_blocks()
2116 		else if (amdgpu_device_has_dc_support(adev))  in cik_set_ip_blocks()
2117 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in cik_set_ip_blocks()
2120 			amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);  in cik_set_ip_blocks()
2121 		amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);  in cik_set_ip_blocks()
2122 		amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);  in cik_set_ip_blocks()
2125 		amdgpu_device_ip_block_add(adev, &cik_common_ip_block);  in cik_set_ip_blocks()
2126 		amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);  in cik_set_ip_blocks()
2127 		amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);  in cik_set_ip_blocks()
2128 		amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);  in cik_set_ip_blocks()
2129 		amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);  in cik_set_ip_blocks()
2130 		amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);  in cik_set_ip_blocks()
2131 		if (adev->enable_virtual_display)  in cik_set_ip_blocks()
2132 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in cik_set_ip_blocks()
2134 		else if (amdgpu_device_has_dc_support(adev))  in cik_set_ip_blocks()
2135 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in cik_set_ip_blocks()
2138 			amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);  in cik_set_ip_blocks()
2140 		amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);  in cik_set_ip_blocks()
2141 		amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);  in cik_set_ip_blocks()
2145 		amdgpu_device_ip_block_add(adev, &cik_common_ip_block);  in cik_set_ip_blocks()
2146 		amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);  in cik_set_ip_blocks()
2147 		amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);  in cik_set_ip_blocks()
2148 		amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);  in cik_set_ip_blocks()
2149 		amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);  in cik_set_ip_blocks()
2150 		amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);  in cik_set_ip_blocks()
2151 		if (adev->enable_virtual_display)  in cik_set_ip_blocks()
2152 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in cik_set_ip_blocks()
2154 		else if (amdgpu_device_has_dc_support(adev))  in cik_set_ip_blocks()
2155 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in cik_set_ip_blocks()
2158 			amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);  in cik_set_ip_blocks()
2159 		amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);  in cik_set_ip_blocks()
2160 		amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);  in cik_set_ip_blocks()