Lines Matching refs:adev
37 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, in amdgpu_gfx_mec_queue_to_bit() argument
42 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
43 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
44 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
50 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit, in amdgpu_gfx_bit_to_mec_queue() argument
53 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_bit_to_mec_queue()
54 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_mec_queue()
55 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_mec_queue()
56 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_mec_queue()
57 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_mec_queue()
61 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, in amdgpu_gfx_is_mec_queue_enabled() argument
64 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue), in amdgpu_gfx_is_mec_queue_enabled()
65 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
68 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, in amdgpu_gfx_me_queue_to_bit() argument
73 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
74 * adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_me_queue_to_bit()
75 bit += pipe * adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_me_queue_to_bit()
81 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, in amdgpu_gfx_bit_to_me_queue() argument
84 *queue = bit % adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_bit_to_me_queue()
85 *pipe = (bit / adev->gfx.me.num_queue_per_pipe) in amdgpu_gfx_bit_to_me_queue()
86 % adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_bit_to_me_queue()
87 *me = (bit / adev->gfx.me.num_queue_per_pipe) in amdgpu_gfx_bit_to_me_queue()
88 / adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_bit_to_me_queue()
91 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, in amdgpu_gfx_is_me_queue_enabled() argument
94 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue), in amdgpu_gfx_is_me_queue_enabled()
95 adev->gfx.me.queue_bitmap); in amdgpu_gfx_is_me_queue_enabled()
107 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg) in amdgpu_gfx_scratch_get() argument
111 i = ffs(adev->gfx.scratch.free_mask); in amdgpu_gfx_scratch_get()
112 if (i != 0 && i <= adev->gfx.scratch.num_reg) { in amdgpu_gfx_scratch_get()
114 adev->gfx.scratch.free_mask &= ~(1u << i); in amdgpu_gfx_scratch_get()
115 *reg = adev->gfx.scratch.reg_base + i; in amdgpu_gfx_scratch_get()
129 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg) in amdgpu_gfx_scratch_free() argument
131 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); in amdgpu_gfx_scratch_free()
178 static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) in amdgpu_gfx_is_multipipe_capable() argument
188 if (adev->asic_type == CHIP_POLARIS11) in amdgpu_gfx_is_multipipe_capable()
191 return adev->gfx.mec.num_mec > 1; in amdgpu_gfx_is_multipipe_capable()
194 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) in amdgpu_gfx_compute_queue_acquire() argument
197 bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev); in amdgpu_gfx_compute_queue_acquire()
201 queue = i % adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_compute_queue_acquire()
202 pipe = (i / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_compute_queue_acquire()
203 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_compute_queue_acquire()
204 mec = (i / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_compute_queue_acquire()
205 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_compute_queue_acquire()
208 if (mec >= adev->gfx.mec.num_mec) in amdgpu_gfx_compute_queue_acquire()
214 set_bit(i, adev->gfx.mec.queue_bitmap); in amdgpu_gfx_compute_queue_acquire()
218 set_bit(i, adev->gfx.mec.queue_bitmap); in amdgpu_gfx_compute_queue_acquire()
223 adev->gfx.num_compute_rings = in amdgpu_gfx_compute_queue_acquire()
224 bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in amdgpu_gfx_compute_queue_acquire()
228 if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS)) in amdgpu_gfx_compute_queue_acquire()
229 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in amdgpu_gfx_compute_queue_acquire()
232 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev) in amdgpu_gfx_graphics_queue_acquire() argument
237 queue = i % adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_graphics_queue_acquire()
238 pipe = (i / adev->gfx.me.num_queue_per_pipe) in amdgpu_gfx_graphics_queue_acquire()
239 % adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_graphics_queue_acquire()
240 me = (i / adev->gfx.me.num_queue_per_pipe) in amdgpu_gfx_graphics_queue_acquire()
241 / adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_graphics_queue_acquire()
243 if (me >= adev->gfx.me.num_me) in amdgpu_gfx_graphics_queue_acquire()
248 set_bit(i, adev->gfx.me.queue_bitmap); in amdgpu_gfx_graphics_queue_acquire()
252 adev->gfx.num_gfx_rings = in amdgpu_gfx_graphics_queue_acquire()
253 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in amdgpu_gfx_graphics_queue_acquire()
256 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, in amdgpu_gfx_kiq_acquire() argument
262 queue_bit = adev->gfx.mec.num_mec in amdgpu_gfx_kiq_acquire()
263 * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_kiq_acquire()
264 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_kiq_acquire()
267 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) in amdgpu_gfx_kiq_acquire()
270 amdgpu_gfx_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); in amdgpu_gfx_kiq_acquire()
287 dev_err(adev->dev, "Failed to find a queue for KIQ\n"); in amdgpu_gfx_kiq_acquire()
291 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, in amdgpu_gfx_kiq_init_ring() argument
295 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init_ring()
300 r = amdgpu_device_wb_get(adev, &adev->virt.reg_val_offs); in amdgpu_gfx_kiq_init_ring()
304 ring->adev = NULL; in amdgpu_gfx_kiq_init_ring()
307 ring->doorbell_index = adev->doorbell_index.kiq; in amdgpu_gfx_kiq_init_ring()
309 r = amdgpu_gfx_kiq_acquire(adev, ring); in amdgpu_gfx_kiq_init_ring()
315 r = amdgpu_ring_init(adev, ring, 1024, in amdgpu_gfx_kiq_init_ring()
318 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); in amdgpu_gfx_kiq_init_ring()
326 amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs); in amdgpu_gfx_kiq_free_ring()
330 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev) in amdgpu_gfx_kiq_fini() argument
332 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_fini()
337 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, in amdgpu_gfx_kiq_init() argument
342 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init()
344 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, in amdgpu_gfx_kiq_init()
348 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); in amdgpu_gfx_kiq_init()
356 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); in amdgpu_gfx_kiq_init()
364 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, in amdgpu_gfx_mqd_sw_init() argument
371 ring = &adev->gfx.kiq.ring; in amdgpu_gfx_mqd_sw_init()
378 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, in amdgpu_gfx_mqd_sw_init()
382 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); in amdgpu_gfx_mqd_sw_init()
387 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL); in amdgpu_gfx_mqd_sw_init()
388 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) in amdgpu_gfx_mqd_sw_init()
389 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
392 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { in amdgpu_gfx_mqd_sw_init()
394 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in amdgpu_gfx_mqd_sw_init()
395 ring = &adev->gfx.gfx_ring[i]; in amdgpu_gfx_mqd_sw_init()
397 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, in amdgpu_gfx_mqd_sw_init()
401 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); in amdgpu_gfx_mqd_sw_init()
406 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); in amdgpu_gfx_mqd_sw_init()
407 if (!adev->gfx.me.mqd_backup[i]) in amdgpu_gfx_mqd_sw_init()
408 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
414 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_mqd_sw_init()
415 ring = &adev->gfx.compute_ring[i]; in amdgpu_gfx_mqd_sw_init()
417 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, in amdgpu_gfx_mqd_sw_init()
421 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); in amdgpu_gfx_mqd_sw_init()
426 adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); in amdgpu_gfx_mqd_sw_init()
427 if (!adev->gfx.mec.mqd_backup[i]) in amdgpu_gfx_mqd_sw_init()
428 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
435 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev) in amdgpu_gfx_mqd_sw_fini() argument
440 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { in amdgpu_gfx_mqd_sw_fini()
441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in amdgpu_gfx_mqd_sw_fini()
442 ring = &adev->gfx.gfx_ring[i]; in amdgpu_gfx_mqd_sw_fini()
443 kfree(adev->gfx.me.mqd_backup[i]); in amdgpu_gfx_mqd_sw_fini()
450 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_mqd_sw_fini()
451 ring = &adev->gfx.compute_ring[i]; in amdgpu_gfx_mqd_sw_fini()
452 kfree(adev->gfx.mec.mqd_backup[i]); in amdgpu_gfx_mqd_sw_fini()
458 ring = &adev->gfx.kiq.ring; in amdgpu_gfx_mqd_sw_fini()
459 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) in amdgpu_gfx_mqd_sw_fini()
460 kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]); in amdgpu_gfx_mqd_sw_fini()
461 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); in amdgpu_gfx_mqd_sw_fini()
467 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) in amdgpu_gfx_disable_kcq() argument
469 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_disable_kcq()
477 adev->gfx.num_compute_rings)) in amdgpu_gfx_disable_kcq()
480 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_gfx_disable_kcq()
481 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i], in amdgpu_gfx_disable_kcq()
487 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) in amdgpu_gfx_enable_kcq() argument
489 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_enable_kcq()
490 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in amdgpu_gfx_enable_kcq()
498 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) in amdgpu_gfx_enable_kcq()
516 adev->gfx.num_compute_rings + in amdgpu_gfx_enable_kcq()
524 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_gfx_enable_kcq()
525 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]); in amdgpu_gfx_enable_kcq()
545 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) in amdgpu_gfx_off_ctrl() argument
547 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in amdgpu_gfx_off_ctrl()
550 if (!is_support_sw_smu(adev) && in amdgpu_gfx_off_ctrl()
551 (!adev->powerplay.pp_funcs || in amdgpu_gfx_off_ctrl()
552 !adev->powerplay.pp_funcs->set_powergating_by_smu)) in amdgpu_gfx_off_ctrl()
556 mutex_lock(&adev->gfx.gfx_off_mutex); in amdgpu_gfx_off_ctrl()
559 adev->gfx.gfx_off_req_count++; in amdgpu_gfx_off_ctrl()
560 else if (adev->gfx.gfx_off_req_count > 0) in amdgpu_gfx_off_ctrl()
561 adev->gfx.gfx_off_req_count--; in amdgpu_gfx_off_ctrl()
563 if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { in amdgpu_gfx_off_ctrl()
564 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE); in amdgpu_gfx_off_ctrl()
565 } else if (!enable && adev->gfx.gfx_off_state) { in amdgpu_gfx_off_ctrl()
566 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) in amdgpu_gfx_off_ctrl()
567 adev->gfx.gfx_off_state = false; in amdgpu_gfx_off_ctrl()
570 mutex_unlock(&adev->gfx.gfx_off_mutex); in amdgpu_gfx_off_ctrl()