85 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)  in vi_pcie_rreg()  argument
90 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in vi_pcie_rreg()
94 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in vi_pcie_rreg()
98 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_pcie_wreg()  argument
102 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in vi_pcie_wreg()
107 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in vi_pcie_wreg()
110 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)  in vi_smc_rreg()  argument
115 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in vi_smc_rreg()
118 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in vi_smc_rreg()
122 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_smc_wreg()  argument
126 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in vi_smc_wreg()
129 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in vi_smc_wreg()
136 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)  in cz_smc_rreg()  argument
141 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cz_smc_rreg()
144 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cz_smc_rreg()
148 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cz_smc_wreg()  argument
152 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cz_smc_wreg()
155 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cz_smc_wreg()
158 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)  in vi_uvd_ctx_rreg()  argument
163 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in vi_uvd_ctx_rreg()
166 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in vi_uvd_ctx_rreg()
170 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_uvd_ctx_wreg()  argument
174 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in vi_uvd_ctx_wreg()
177 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in vi_uvd_ctx_wreg()
180 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)  in vi_didt_rreg()  argument
185 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in vi_didt_rreg()
188 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in vi_didt_rreg()
192 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_didt_wreg()  argument
196 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in vi_didt_wreg()
199 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in vi_didt_wreg()
202 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)  in vi_gc_cac_rreg()  argument
207 	spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);  in vi_gc_cac_rreg()
210 	spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);  in vi_gc_cac_rreg()
214 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_gc_cac_wreg()  argument
218 	spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);  in vi_gc_cac_wreg()
221 	spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);  in vi_gc_cac_wreg()
272 static void vi_init_golden_registers(struct amdgpu_device *adev)  in vi_init_golden_registers()  argument
275 	mutex_lock(&adev->grbm_idx_mutex);  in vi_init_golden_registers()
277 	if (amdgpu_sriov_vf(adev)) {  in vi_init_golden_registers()
278 		xgpu_vi_init_golden_registers(adev);  in vi_init_golden_registers()
279 		mutex_unlock(&adev->grbm_idx_mutex);  in vi_init_golden_registers()
283 	switch (adev->asic_type) {  in vi_init_golden_registers()
285 		amdgpu_device_program_register_sequence(adev,  in vi_init_golden_registers()
290 		amdgpu_device_program_register_sequence(adev,  in vi_init_golden_registers()
295 		amdgpu_device_program_register_sequence(adev,  in vi_init_golden_registers()
300 		amdgpu_device_program_register_sequence(adev,  in vi_init_golden_registers()
305 		amdgpu_device_program_register_sequence(adev,  in vi_init_golden_registers()
316 	mutex_unlock(&adev->grbm_idx_mutex);  in vi_init_golden_registers()
327 static u32 vi_get_xclk(struct amdgpu_device *adev)  in vi_get_xclk()  argument
329 	u32 reference_clock = adev->clock.spll.reference_freq;  in vi_get_xclk()
332 	if (adev->flags & AMD_IS_APU)  in vi_get_xclk()
359 void vi_srbm_select(struct amdgpu_device *adev,  in vi_srbm_select()  argument
370 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)  in vi_vga_set_state()  argument
375 static bool vi_read_disabled_bios(struct amdgpu_device *adev)  in vi_read_disabled_bios()  argument
385 	if (adev->mode_info.num_crtc) {  in vi_read_disabled_bios()
394 	if (adev->mode_info.num_crtc) {  in vi_read_disabled_bios()
407 	r = amdgpu_read_bios(adev);  in vi_read_disabled_bios()
411 	if (adev->mode_info.num_crtc) {  in vi_read_disabled_bios()
420 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,  in vi_read_bios_from_rom()  argument
432 	if (adev->flags & AMD_IS_APU)  in vi_read_bios_from_rom()
438 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in vi_read_bios_from_rom()
446 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in vi_read_bios_from_rom()
451 static void vi_detect_hw_virtualization(struct amdgpu_device *adev)  in vi_detect_hw_virtualization()  argument
455 	if (adev->asic_type == CHIP_TONGA ||  in vi_detect_hw_virtualization()
456 	    adev->asic_type == CHIP_FIJI) {  in vi_detect_hw_virtualization()
460 		       adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;  in vi_detect_hw_virtualization()
463 		       adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;  in vi_detect_hw_virtualization()
468 			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;  in vi_detect_hw_virtualization()
551 static uint32_t vi_get_register_value(struct amdgpu_device *adev,  in vi_get_register_value()  argument
562 			return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;  in vi_get_register_value()
564 			return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;  in vi_get_register_value()
566 			return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;  in vi_get_register_value()
568 			return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;  in vi_get_register_value()
571 		mutex_lock(&adev->grbm_idx_mutex);  in vi_get_register_value()
573 			amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);  in vi_get_register_value()
578 			amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);  in vi_get_register_value()
579 		mutex_unlock(&adev->grbm_idx_mutex);  in vi_get_register_value()
586 			return adev->gfx.config.gb_addr_config;  in vi_get_register_value()
588 			return adev->gfx.config.mc_arb_ramcfg;  in vi_get_register_value()
622 			return adev->gfx.config.tile_mode_array[idx];  in vi_get_register_value()
640 			return adev->gfx.config.macrotile_mode_array[idx];  in vi_get_register_value()
647 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,  in vi_read_register()  argument
659 		*value = vi_get_register_value(adev, indexed, se_num, sh_num,  in vi_read_register()
666 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)  in vi_gpu_pci_config_reset()  argument
670 	dev_info(adev->dev, "GPU pci config reset\n");  in vi_gpu_pci_config_reset()
673 	pci_clear_master(adev->pdev);  in vi_gpu_pci_config_reset()
675 	amdgpu_device_pci_config_reset(adev);  in vi_gpu_pci_config_reset()
680 	for (i = 0; i < adev->usec_timeout; i++) {  in vi_gpu_pci_config_reset()
683 			pci_set_master(adev->pdev);  in vi_gpu_pci_config_reset()
684 			adev->has_hw_reset = true;  in vi_gpu_pci_config_reset()
701 static int vi_asic_reset(struct amdgpu_device *adev)  in vi_asic_reset()  argument
705 	amdgpu_atombios_scratch_regs_engine_hung(adev, true);  in vi_asic_reset()
707 	r = vi_gpu_pci_config_reset(adev);  in vi_asic_reset()
709 	amdgpu_atombios_scratch_regs_engine_hung(adev, false);  in vi_asic_reset()
715 vi_asic_reset_method(struct amdgpu_device *adev)  in vi_asic_reset_method()  argument
720 static u32 vi_get_config_memsize(struct amdgpu_device *adev)  in vi_get_config_memsize()  argument
725 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,  in vi_set_uvd_clock()  argument
732 	r = amdgpu_atombios_get_clock_dividers(adev,  in vi_set_uvd_clock()
740 	if (adev->flags & AMD_IS_APU)  in vi_set_uvd_clock()
750 		if (adev->flags & AMD_IS_APU) {  in vi_set_uvd_clock()
771 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)  in vi_set_uvd_clocks()  argument
775 	if (adev->flags & AMD_IS_APU) {  in vi_set_uvd_clocks()
776 		r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);  in vi_set_uvd_clocks()
780 		r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);  in vi_set_uvd_clocks()
784 		r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);  in vi_set_uvd_clocks()
788 		r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);  in vi_set_uvd_clocks()
796 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)  in vi_set_vce_clocks()  argument
806 	if (adev->flags & AMD_IS_APU) {  in vi_set_vce_clocks()
818 	r = amdgpu_atombios_get_clock_dividers(adev,  in vi_set_vce_clocks()
850 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)  in vi_pcie_gen3_enable()  argument
852 	if (pci_is_root_bus(adev->pdev->bus))  in vi_pcie_gen3_enable()
858 	if (adev->flags & AMD_IS_APU)  in vi_pcie_gen3_enable()
861 	if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |  in vi_pcie_gen3_enable()
868 static void vi_program_aspm(struct amdgpu_device *adev)  in vi_program_aspm()  argument
877 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,  in vi_enable_doorbell_aperture()  argument
883 	if (adev->flags & AMD_IS_APU)  in vi_enable_doorbell_aperture()
899 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)  in vi_get_rev_id()  argument
901 	if (adev->flags & AMD_IS_APU)  in vi_get_rev_id()
909 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)  in vi_flush_hdp()  argument
919 static void vi_invalidate_hdp(struct amdgpu_device *adev,  in vi_invalidate_hdp()  argument
930 static bool vi_need_full_reset(struct amdgpu_device *adev)  in vi_need_full_reset()  argument
932 	switch (adev->asic_type) {  in vi_need_full_reset()
951 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,  in vi_get_pcie_usage()  argument
961 	if (adev->flags & AMD_IS_APU)  in vi_get_pcie_usage()
997 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)  in vi_get_pcie_replay_count()  argument
1009 static bool vi_need_reset_on_init(struct amdgpu_device *adev)  in vi_need_reset_on_init()  argument
1013 	if (adev->flags & AMD_IS_APU)  in vi_need_reset_on_init()
1052 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_early_init()  local
1054 	if (adev->flags & AMD_IS_APU) {  in vi_common_early_init()
1055 		adev->smc_rreg = &cz_smc_rreg;  in vi_common_early_init()
1056 		adev->smc_wreg = &cz_smc_wreg;  in vi_common_early_init()
1058 		adev->smc_rreg = &vi_smc_rreg;  in vi_common_early_init()
1059 		adev->smc_wreg = &vi_smc_wreg;  in vi_common_early_init()
1061 	adev->pcie_rreg = &vi_pcie_rreg;  in vi_common_early_init()
1062 	adev->pcie_wreg = &vi_pcie_wreg;  in vi_common_early_init()
1063 	adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;  in vi_common_early_init()
1064 	adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;  in vi_common_early_init()
1065 	adev->didt_rreg = &vi_didt_rreg;  in vi_common_early_init()
1066 	adev->didt_wreg = &vi_didt_wreg;  in vi_common_early_init()
1067 	adev->gc_cac_rreg = &vi_gc_cac_rreg;  in vi_common_early_init()
1068 	adev->gc_cac_wreg = &vi_gc_cac_wreg;  in vi_common_early_init()
1070 	adev->asic_funcs = &vi_asic_funcs;  in vi_common_early_init()
1072 	adev->rev_id = vi_get_rev_id(adev);  in vi_common_early_init()
1073 	adev->external_rev_id = 0xFF;  in vi_common_early_init()
1074 	switch (adev->asic_type) {  in vi_common_early_init()
1076 		adev->cg_flags = 0;  in vi_common_early_init()
1077 		adev->pg_flags = 0;  in vi_common_early_init()
1078 		adev->external_rev_id = 0x1;  in vi_common_early_init()
1081 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in vi_common_early_init()
1098 		adev->pg_flags = 0;  in vi_common_early_init()
1099 		adev->external_rev_id = adev->rev_id + 0x3c;  in vi_common_early_init()
1102 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in vi_common_early_init()
1115 		adev->pg_flags = 0;  in vi_common_early_init()
1116 		adev->external_rev_id = adev->rev_id + 0x14;  in vi_common_early_init()
1119 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in vi_common_early_init()
1138 		adev->pg_flags = 0;  in vi_common_early_init()
1139 		adev->external_rev_id = adev->rev_id + 0x5A;  in vi_common_early_init()
1142 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in vi_common_early_init()
1161 		adev->pg_flags = 0;  in vi_common_early_init()
1162 		adev->external_rev_id = adev->rev_id + 0x50;  in vi_common_early_init()
1165 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in vi_common_early_init()
1184 		adev->pg_flags = 0;  in vi_common_early_init()
1185 		adev->external_rev_id = adev->rev_id + 0x64;  in vi_common_early_init()
1188 		adev->cg_flags = 0;  in vi_common_early_init()
1208 		adev->pg_flags = 0;  in vi_common_early_init()
1209 		adev->external_rev_id = adev->rev_id + 0x6E;  in vi_common_early_init()
1212 		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |  in vi_common_early_init()
1228 		adev->pg_flags = 0;  in vi_common_early_init()
1229 		if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {  in vi_common_early_init()
1230 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |  in vi_common_early_init()
1236 		adev->external_rev_id = adev->rev_id + 0x1;  in vi_common_early_init()
1239 		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |  in vi_common_early_init()
1253 		adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |  in vi_common_early_init()
1259 		adev->external_rev_id = adev->rev_id + 0x61;  in vi_common_early_init()
1266 	if (amdgpu_sriov_vf(adev)) {  in vi_common_early_init()
1267 		amdgpu_virt_init_setting(adev);  in vi_common_early_init()
1268 		xgpu_vi_mailbox_set_irq_funcs(adev);  in vi_common_early_init()
1276 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_late_init()  local
1278 	if (amdgpu_sriov_vf(adev))  in vi_common_late_init()
1279 		xgpu_vi_mailbox_get_irq(adev);  in vi_common_late_init()
1286 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_sw_init()  local
1288 	if (amdgpu_sriov_vf(adev))  in vi_common_sw_init()
1289 		xgpu_vi_mailbox_add_irq_id(adev);  in vi_common_sw_init()
1301 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_hw_init()  local
1304 	vi_init_golden_registers(adev);  in vi_common_hw_init()
1306 	vi_pcie_gen3_enable(adev);  in vi_common_hw_init()
1308 	vi_program_aspm(adev);  in vi_common_hw_init()
1310 	vi_enable_doorbell_aperture(adev, true);  in vi_common_hw_init()
1317 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_hw_fini()  local
1320 	vi_enable_doorbell_aperture(adev, false);  in vi_common_hw_fini()
1322 	if (amdgpu_sriov_vf(adev))  in vi_common_hw_fini()
1323 		xgpu_vi_mailbox_put_irq(adev);  in vi_common_hw_fini()
1330 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_suspend()  local
1332 	return vi_common_hw_fini(adev);  in vi_common_suspend()
1337 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_resume()  local
1339 	return vi_common_hw_init(adev);  in vi_common_resume()
1357 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,  in vi_update_bif_medium_grain_light_sleep()  argument
1364 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))  in vi_update_bif_medium_grain_light_sleep()
1377 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,  in vi_update_hdp_medium_grain_clock_gating()  argument
1384 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))  in vi_update_hdp_medium_grain_clock_gating()
1393 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,  in vi_update_hdp_light_sleep()  argument
1400 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))  in vi_update_hdp_light_sleep()
1409 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,  in vi_update_drm_light_sleep()  argument
1416 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))  in vi_update_drm_light_sleep()
1426 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,  in vi_update_rom_medium_grain_clock_gating()  argument
1433 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))  in vi_update_rom_medium_grain_clock_gating()
1449 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_set_clockgating_state_by_smu()  local
1451 	if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {  in vi_common_set_clockgating_state_by_smu()
1452 		if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {  in vi_common_set_clockgating_state_by_smu()
1456 		if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {  in vi_common_set_clockgating_state_by_smu()
1466 		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)  in vi_common_set_clockgating_state_by_smu()
1467 			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);  in vi_common_set_clockgating_state_by_smu()
1470 	if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {  in vi_common_set_clockgating_state_by_smu()
1471 		if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {  in vi_common_set_clockgating_state_by_smu()
1475 		if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {  in vi_common_set_clockgating_state_by_smu()
1485 		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)  in vi_common_set_clockgating_state_by_smu()
1486 			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);  in vi_common_set_clockgating_state_by_smu()
1489 	if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {  in vi_common_set_clockgating_state_by_smu()
1490 		if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {  in vi_common_set_clockgating_state_by_smu()
1494 		if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {  in vi_common_set_clockgating_state_by_smu()
1504 		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)  in vi_common_set_clockgating_state_by_smu()
1505 			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);  in vi_common_set_clockgating_state_by_smu()
1509 	if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {  in vi_common_set_clockgating_state_by_smu()
1519 		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)  in vi_common_set_clockgating_state_by_smu()
1520 			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);  in vi_common_set_clockgating_state_by_smu()
1522 	if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {  in vi_common_set_clockgating_state_by_smu()
1532 		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)  in vi_common_set_clockgating_state_by_smu()
1533 			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);  in vi_common_set_clockgating_state_by_smu()
1536 	if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {  in vi_common_set_clockgating_state_by_smu()
1547 		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)  in vi_common_set_clockgating_state_by_smu()
1548 			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);  in vi_common_set_clockgating_state_by_smu()
1551 	if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {  in vi_common_set_clockgating_state_by_smu()
1562 		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)  in vi_common_set_clockgating_state_by_smu()
1563 			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);  in vi_common_set_clockgating_state_by_smu()
1571 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_set_clockgating_state()  local
1573 	if (amdgpu_sriov_vf(adev))  in vi_common_set_clockgating_state()
1576 	switch (adev->asic_type) {  in vi_common_set_clockgating_state()
1578 		vi_update_bif_medium_grain_light_sleep(adev,  in vi_common_set_clockgating_state()
1580 		vi_update_hdp_medium_grain_clock_gating(adev,  in vi_common_set_clockgating_state()
1582 		vi_update_hdp_light_sleep(adev,  in vi_common_set_clockgating_state()
1584 		vi_update_rom_medium_grain_clock_gating(adev,  in vi_common_set_clockgating_state()
1589 		vi_update_bif_medium_grain_light_sleep(adev,  in vi_common_set_clockgating_state()
1591 		vi_update_hdp_medium_grain_clock_gating(adev,  in vi_common_set_clockgating_state()
1593 		vi_update_hdp_light_sleep(adev,  in vi_common_set_clockgating_state()
1595 		vi_update_drm_light_sleep(adev,  in vi_common_set_clockgating_state()
1603 		vi_common_set_clockgating_state_by_smu(adev, state);  in vi_common_set_clockgating_state()
1618 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_get_clockgating_state()  local
1621 	if (amdgpu_sriov_vf(adev))  in vi_common_get_clockgating_state()
1672 int vi_set_ip_blocks(struct amdgpu_device *adev)  in vi_set_ip_blocks()  argument
1675 	vi_detect_hw_virtualization(adev);  in vi_set_ip_blocks()
1677 	if (amdgpu_sriov_vf(adev))  in vi_set_ip_blocks()
1678 		adev->virt.ops = &xgpu_vi_virt_ops;  in vi_set_ip_blocks()
1680 	switch (adev->asic_type) {  in vi_set_ip_blocks()
1683 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);  in vi_set_ip_blocks()
1684 		amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);  in vi_set_ip_blocks()
1685 		amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);  in vi_set_ip_blocks()
1686 		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);  in vi_set_ip_blocks()
1687 		amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);  in vi_set_ip_blocks()
1688 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in vi_set_ip_blocks()
1689 		if (adev->enable_virtual_display)  in vi_set_ip_blocks()
1690 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in vi_set_ip_blocks()
1693 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);  in vi_set_ip_blocks()
1694 		amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);  in vi_set_ip_blocks()
1695 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);  in vi_set_ip_blocks()
1696 		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);  in vi_set_ip_blocks()
1697 		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);  in vi_set_ip_blocks()
1698 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in vi_set_ip_blocks()
1699 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))  in vi_set_ip_blocks()
1700 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in vi_set_ip_blocks()
1702 		else if (amdgpu_device_has_dc_support(adev))  in vi_set_ip_blocks()
1703 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in vi_set_ip_blocks()
1706 			amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);  in vi_set_ip_blocks()
1707 		if (!amdgpu_sriov_vf(adev)) {  in vi_set_ip_blocks()
1708 			amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);  in vi_set_ip_blocks()
1709 			amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);  in vi_set_ip_blocks()
1713 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);  in vi_set_ip_blocks()
1714 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);  in vi_set_ip_blocks()
1715 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);  in vi_set_ip_blocks()
1716 		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);  in vi_set_ip_blocks()
1717 		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);  in vi_set_ip_blocks()
1718 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in vi_set_ip_blocks()
1719 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))  in vi_set_ip_blocks()
1720 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in vi_set_ip_blocks()
1722 		else if (amdgpu_device_has_dc_support(adev))  in vi_set_ip_blocks()
1723 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in vi_set_ip_blocks()
1726 			amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);  in vi_set_ip_blocks()
1727 		if (!amdgpu_sriov_vf(adev)) {  in vi_set_ip_blocks()
1728 			amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);  in vi_set_ip_blocks()
1729 			amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);  in vi_set_ip_blocks()
1736 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);  in vi_set_ip_blocks()
1737 		amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);  in vi_set_ip_blocks()
1738 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);  in vi_set_ip_blocks()
1739 		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);  in vi_set_ip_blocks()
1740 		amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);  in vi_set_ip_blocks()
1741 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in vi_set_ip_blocks()
1742 		if (adev->enable_virtual_display)  in vi_set_ip_blocks()
1743 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in vi_set_ip_blocks()
1745 		else if (amdgpu_device_has_dc_support(adev))  in vi_set_ip_blocks()
1746 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in vi_set_ip_blocks()
1749 			amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);  in vi_set_ip_blocks()
1750 		amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);  in vi_set_ip_blocks()
1751 		amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);  in vi_set_ip_blocks()
1754 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);  in vi_set_ip_blocks()
1755 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);  in vi_set_ip_blocks()
1756 		amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);  in vi_set_ip_blocks()
1757 		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);  in vi_set_ip_blocks()
1758 		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);  in vi_set_ip_blocks()
1759 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in vi_set_ip_blocks()
1760 		if (adev->enable_virtual_display)  in vi_set_ip_blocks()
1761 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in vi_set_ip_blocks()
1763 		else if (amdgpu_device_has_dc_support(adev))  in vi_set_ip_blocks()
1764 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in vi_set_ip_blocks()
1767 			amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);  in vi_set_ip_blocks()
1768 		amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);  in vi_set_ip_blocks()
1769 		amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);  in vi_set_ip_blocks()
1771 		amdgpu_device_ip_block_add(adev, &acp_ip_block);  in vi_set_ip_blocks()
1775 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);  in vi_set_ip_blocks()
1776 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);  in vi_set_ip_blocks()
1777 		amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);  in vi_set_ip_blocks()
1778 		amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);  in vi_set_ip_blocks()
1779 		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);  in vi_set_ip_blocks()
1780 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in vi_set_ip_blocks()
1781 		if (adev->enable_virtual_display)  in vi_set_ip_blocks()
1782 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in vi_set_ip_blocks()
1784 		else if (amdgpu_device_has_dc_support(adev))  in vi_set_ip_blocks()
1785 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in vi_set_ip_blocks()
1788 			amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);  in vi_set_ip_blocks()
1789 		amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);  in vi_set_ip_blocks()
1790 		amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);  in vi_set_ip_blocks()
1792 		amdgpu_device_ip_block_add(adev, &acp_ip_block);  in vi_set_ip_blocks()
1803 void legacy_doorbell_index_init(struct amdgpu_device *adev)  in legacy_doorbell_index_init()  argument
1805 	adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;  in legacy_doorbell_index_init()
1806 	adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;  in legacy_doorbell_index_init()
1807 	adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;  in legacy_doorbell_index_init()
1808 	adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;  in legacy_doorbell_index_init()
1809 	adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;  in legacy_doorbell_index_init()
1810 	adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;  in legacy_doorbell_index_init()
1811 	adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;  in legacy_doorbell_index_init()
1812 	adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;  in legacy_doorbell_index_init()
1813 	adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;  in legacy_doorbell_index_init()
1814 	adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;  in legacy_doorbell_index_init()
1815 	adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;  in legacy_doorbell_index_init()
1816 	adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;  in legacy_doorbell_index_init()
1817 	adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;  in legacy_doorbell_index_init()
1818 	adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;  in legacy_doorbell_index_init()