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/Linux-v5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
65 /* get tx dma good octet counter */
68 /* get tx dma good packet counter */
89 /* get msm tx errors counter register */
92 /* get msm tx unicast frames counter register */
95 /* get msm tx multicast frames counter register */
98 /* get msm tx broadcast frames counter register */
101 /* get msm tx multicast octets counter register 1 */
[all …]
/Linux-v5.10/sound/arm/
Daaci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
20 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
23 #define AACI_IE 0x010 /* 7 bits Int Enable */
36 #define AACI_SLIEN 0x070 /* slot interrupt enable */
49 * TX/RX fifo control register (CR). P48
51 #define CR_FEN (1 << 16) /* fifo enable */
69 #define CR_EN (1 << 0) /* transmit enable */
76 #define SR_TXU (1 << 9) /* tx underrun */
78 #define SR_TXB (1 << 7) /* tx busy */
[all …]
/Linux-v5.10/drivers/net/wan/
Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
[all …]
Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
42 #define IER0 0x74 /* Interrupt Enable Register 0 */
43 #define IER1 0x78 /* Interrupt Enable Register 1 */
48 #define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */
50 #define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */
53 #define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */
66 #define TXS 0x13d /* TX clock source */
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/Linux-v5.10/drivers/media/rc/
Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
24 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
25 #define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
30 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
31 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
32 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
39 #define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */
40 #define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */
43 #define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
[all …]
Dene_ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #include <media/rc-core.h>
37 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI); in ene_set_reg_addr()
38 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO); in ene_set_reg_addr()
46 retval = inb(dev->hw_io + ENE_IO); in ene_read_reg()
54 dbg_regs("reg %04x <- %02x", reg, value); in ene_write_reg()
56 outb(value, dev->hw_io + ENE_IO); in ene_write_reg()
64 outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO); in ene_set_reg_mask()
72 outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO); in ene_clear_reg_mask()
100 dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) + in ene_hw_detect()
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/Linux-v5.10/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
33 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
36 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
39 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
52 /* Enable Length/Type error checking for incoming frames. When this option is
60 /* Enable the transmitter. Default: enabled (set) */
63 /* Enable the receiver. Default: enabled (set) */
107 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
108 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
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/Linux-v5.10/drivers/net/ethernet/broadcom/
Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */
10 #define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */
13 #define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */
14 #define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
44 #define ISTAT_TX 0x01000000 /* TX Interrupt */
56 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */
59 #define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
66 #define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
[all …]
/Linux-v5.10/drivers/net/ethernet/sun/
Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
45 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
96 * This register is used to perform a global reset of the RX and TX portions
97 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
[all …]
Dsunqe.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
22 #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
45 /* The following registers are for per-qe channel information/status. */
49 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
51 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
56 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
57 #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
59 #define CREG_PIPG 0x34UL /* Inter-Frame Gap */
69 #define CREG_STAT_LCOLL 0x02000000 /* Late TX Collision */
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/Linux-v5.10/drivers/usb/serial/
Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
22 // above are used internally to indicate that we must enable access
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
32 #define IER 1 // ! Interrupt Enable Register
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
57 #define IER_RX 0x01 // Enable receive interrupt
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/Linux-v5.10/drivers/media/i2c/adv748x/
Dadv748x-csi2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices ADV748X CSI-2 Transmitter
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-ioctl.h>
17 static int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, in adv748x_csi2_set_virtual_channel() argument
20 return tx_write(tx, ADV748X_CSI_VC_REF, vc << ADV748X_CSI_VC_REF_SHIFT); in adv748x_csi2_set_virtual_channel()
26 * @tx: CSI2 private entity
29 * @src_pad: Pad number of source to link to this @tx
30 * @enable: Link enabled flag
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/Linux-v5.10/Documentation/devicetree/bindings/usb/
Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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/Linux-v5.10/drivers/spi/
Dspi-dln2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Diolan DLN-2 USB-SPI adapter
98 * Enable/Disable SPI module. The disable command will wait for transfers to
101 static int dln2_spi_enable(struct dln2_spi *dln2, bool enable) in dln2_spi_enable() argument
107 } tx; in dln2_spi_enable() local
108 unsigned len = sizeof(tx); in dln2_spi_enable()
110 tx.port = dln2->port; in dln2_spi_enable()
112 if (enable) { in dln2_spi_enable()
114 len -= sizeof(tx.wait_for_completion); in dln2_spi_enable()
116 tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE; in dln2_spi_enable()
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/Linux-v5.10/drivers/net/hamradio/
Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
56 #define RxENABLE 0x1 /* Rx Enable */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
69 #define PAR_ENA 0x1 /* Parity Enable */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
89 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
[all …]
/Linux-v5.10/include/uapi/linux/
Dserial_reg.h1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
24 #define UART_IER 1 /* Out: Interrupt Enable Register */
25 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
26 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
28 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
32 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
49 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
55 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
107 #define UART_LCR_PARITY 0x08 /* Parity Enable */
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/Linux-v5.10/drivers/net/ethernet/intel/igb/
De1000_82575.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Receive Descriptor - Advanced */
95 /* Transmit Descriptor - Advanced */
117 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
118 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
134 /* IPSec Encrypt Enable for ESP */
141 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
142 /* Tx Queue Arbitration Priority 0=low, 1=high */
145 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
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/Linux-v5.10/net/ncsi/
Dncsi-pkt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 unsigned char revision; /* NCSI version - 0x01 */
75 /* AEN Enable */
101 unsigned char enable; /* Enable or disable */ member
106 /* Enable VLAN */
125 /* Enable Broadcast Filter */
133 /* Enable Global Multicast Filter */
227 unsigned char mac_enable; /* MAC addr enable flags */
230 __be16 vlan_enable; /* VLAN tag enable flags */
249 __be32 tx_bytes; /* Tx bytes */
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/Linux-v5.10/drivers/media/radio/wl128x/
Dfmdrv_tx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This sub-module of FM driver implements FM TX functionality.
19 if (fmdev->tx_data.aud_mode == mode) in fm_tx_set_stereo_mono()
25 payload = (1 - mode); in fm_tx_set_stereo_mono()
31 fmdev->tx_data.aud_mode = mode; in fm_tx_set_stereo_mono()
115 /* Send command to enable RDS */ in fm_tx_set_rds_mode()
133 fmdev->tx_data.rds.flag = rds_en_dis; in fm_tx_set_rds_mode()
143 if (fmdev->curr_fmmode != FM_MODE_TX) in fm_tx_set_radio_text()
144 return -EPERM; in fm_tx_set_radio_text()
171 if (fmdev->curr_fmmode != FM_MODE_TX) in fm_tx_set_af()
[all …]
/Linux-v5.10/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
42 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
[all …]
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
154 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
156 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
173 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
246 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
[all …]
/Linux-v5.10/drivers/tty/serial/
Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
63 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
75 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
81 #define RxENAB 0x1 /* Rx Enable */
84 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
95 #define PAR_ENAB 0x1 /* Parity Enable */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
[all …]
Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
103 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
108 #define RxENABLE 0x1 /* Rx Enable */
111 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
[all …]
/Linux-v5.10/drivers/net/wireless/broadcom/b43/
Dphy_ht.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
18 #define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */
19 #define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */
31 #define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */
32 #define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */
39 #define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */
42 #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */
43 #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */
44 #define B43_PHY_HT_TXPCTL_N 0x1E8 /* TX power control N num */
[all …]
/Linux-v5.10/arch/m68k/include/asm/
Dm54xxpci.h4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
45 #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
46 #define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
47 #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
48 #define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
49 #define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
50 #define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
51 #define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
52 #define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
53 #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
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