Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
45 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
96 * This register is used to perform a global reset of the RX and TX portions
97 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
101 #define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */
107 /* TX DMA Registers */
108 #define TXDMA_KICK 0x2000UL /* TX Kick Register */
109 #define TXDMA_CFG 0x2004UL /* TX Configuration Register */
110 #define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */
111 #define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */
112 #define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */
113 #define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */
114 #define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */
115 #define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */
116 #define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */
117 #define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */
118 #define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */
119 #define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */
120 #define TXDMA_TXDONE 0x2100UL /* TX Completion Register */
121 #define TXDMA_FADDR 0x2104UL /* TX FIFO Address */
122 #define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */
123 #define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */
124 #define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */
125 #define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */
126 #define TXDMA_FSZ 0x2118UL /* TX FIFO Size */
128 /* TX Kick Register.
130 * This 13-bit register is programmed by the driver to hold the descriptor
134 /* TX Completion Register.
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
142 /* TX Configuration Register.
144 * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature
146 * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors.
148 #define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */
149 #define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */
150 #define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */
151 #define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */
152 #define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */
153 #define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */
154 #define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */
155 #define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */
156 #define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */
157 #define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */
158 #define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */
159 #define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */
160 #define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */
161 #define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/
163 /* TX Descriptor Base Low/High.
166 * of the TX descriptor table. The 11 least significant bits are always
167 * zero. As a result, the TX descriptor table must be 2K aligned.
171 * them later. -DaveM
218 #define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */
220 #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
221 #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
222 #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
223 #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
224 #define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */
225 #define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */
226 #define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */
227 #define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */
228 #define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */
233 #define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */
234 #define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */
235 #define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */
236 #define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */
237 #define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */
238 #define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */
257 * This 13-bit register is written by the host CPU and holds the last
270 * This 13-bit register is updated by GEM to indicate which RX descriptors
291 * This 11-bit read-only register indicates how large, in units of 64-bytes,
297 * them later. -DaveM
301 #define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/
304 #define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */
307 #define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */
310 #define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/
368 /* TX MAC Software Reset Command. */
369 #define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */
372 #define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */
376 * Send_Pause and flow-control
384 /* TX MAC Status Register. */
386 #define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */
410 /* The layout of the MAC_{TX,RX,C}MASK registers is identical to that
411 * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent
414 * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
417 /* TX MAC Configuration Register.
419 * NOTE: The TX MAC Enable bit must be cleared and polled until
423 * a 3 step process 1) Set TX Carrier Extension 2) Set
425 * mode must be enabled when in half-duplex at 1Gbps, else
428 #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */
431 #define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */
437 #define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */
441 * NOTE: The RX MAC Enable bit must be cleared and polled until
444 * Similar rules apply to the Hash Filter Enable bit when
446 * Enable bit when programming the address filter registers.
448 #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */
453 #define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */
454 #define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */
459 #define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */
460 #define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */
468 #define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */
469 #define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */
470 #define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */
476 /* InterPacketGap0 Register. This 8-bit value is used as an extension
478 * timing of the RX-to-TX IPG. This value is ignored and presumed to
479 * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
480 * is cleared in the TX MAC Configuration Register.
487 /* InterPacketGap1 Register. This 8-bit value defines the first 2/3
495 /* InterPacketGap2 Register. This 8-bit value defines the second 1/3
503 /* Slot Time Register. This 10-bit value specifies the slot time
510 /* Minimum Frame Size Register. This 10-bit register specifies the
522 * packets sent in half-duplex gigabit modes.
529 /* PA Size Register. This 10-bit register specifies the number of preamble
536 /* Jam Size Register. This 4-bit register specifies the duration of
542 /* Attempts Limit Register. This 8-bit register specifies the number
552 /* MAX Control Type Register. This 16-bit register specifies the
562 * ethernet MAC of the interface, 16-bits at a time. Register
582 * filter. The Address Filter 2&1 Mask Register denotes the 8-bit
584 * Filter 0 Mask Register denotes the 16-bit mask for the Address
592 /* Statistics Registers. All of these registers are 16-bits and
599 /* Random Number Seed Register. This 10-bit value is used as the
605 /* Pause Timer, read-only. This 16-bit timer is used to time the pause
607 * A non-zero value in this timer indicates that the MAC is currently in
612 #define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */
613 #define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */
614 #define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */
621 /* MIF Bit-Bang Clock. This 1-bit register is used to generate the
623 * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into
630 /* MIF Bit-Bang Data. This 1-bit register is used to generate the
632 * is programmed in the "Bit-Bang" mode. The daa will be steered to the
637 /* MIF Big-Band Output Enable. THis 1-bit register is used to enable
638 * ('1') or disable ('0') the I-directional driver on the MII when the
639 * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled
647 /* MIF Configuration Register. This 15-bit register controls the operation
651 #define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */
652 #define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */
654 #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
655 #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
658 /* MIF Frame/Output Register. This 32-bit register allows the host to
659 * communicate with a transceiver in frame mode (as opposed to big-bang
674 * operating in the poll mode. The poll status field is auto-clearing
680 /* MIF Mask Register. This 16-bit register is used when in poll mode
702 #define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */
705 #define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */
707 #define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit
716 #define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */
718 #define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */
727 #define PCS_MIIADV_ACK 0x00004000 /* Read-only */
728 #define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */
741 #define PCS_CFG_JS 0x00000018 /* Jitter-study:
743 * 1 = high-frequency test pattern
744 * 2 = low-frequency test pattern
747 #define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */
749 /* PCS Interrupt Status Register. This register is self-clearing
758 #define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */
764 #define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */
765 #define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */
769 #define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */
788 #define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */
806 /* MII BCM5400 1000-BASET Control register */
819 /* When it can, GEM internally caches 4 aligned TX descriptors
823 * control word. The same functionality is obtained via the TX-Kick
824 * and TX-Complete registers. As a result, GEM need not write back
825 * updated values to the TX descriptor ring, it only performs reads.
827 * Since TX descriptors are never modified by GEM, the driver can
839 #define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */
854 * Unlike for TX, GEM does update the status word in the RX descriptors
864 * by the host driver just as in the TX descriptor case above.
871 #define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */
880 ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
930 #define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1))
931 #define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1))
934 (((GP)->tx_old <= (GP)->tx_new) ? \
935 (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \
936 (GP)->tx_old - (GP)->tx_new - 1)
939 #define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)
981 unsigned int has_wol : 1; /* chip supports wake-on-lan */
1025 #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \
1026 gp->phy_mii.def && gp->phy_mii.def->ops)