Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */
10 #define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */
13 #define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */
14 #define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
44 #define ISTAT_TX 0x01000000 /* TX Interrupt */
56 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */
59 #define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
66 #define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
71 #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */
72 #define DMATX_CTRL_ENABLE 0x00000001 /* Enable */
74 #define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
77 #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */
78 #define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */
79 #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */
95 #define DMARX_CTRL_ENABLE 0x00000001 /* Enable */
130 #define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */
131 #define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */
132 #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */
137 #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
140 #define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */
166 #define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */
174 #define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */
178 #define B44_TX_CTRL 0x0430UL /* EMAC TX Control */
181 #define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */
183 #define B44_TX_WMARK 0x0434UL /* EMAC TX Watermark */
186 #define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */
187 #define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */
188 #define B44_TX_O 0x0508UL /* MIB TX Octets */
189 #define B44_TX_P 0x050CUL /* MIB TX Packets */
190 #define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */
191 #define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */
192 #define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */
193 #define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Packets */
194 #define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Packets */
195 #define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Packets */
196 #define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Packets */
197 #define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */
198 #define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */
199 #define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */
200 #define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */
201 #define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */
202 #define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */
203 #define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */
204 #define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */
205 #define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */
206 #define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */
207 #define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */
208 #define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */
209 #define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */
232 #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */
287 /* no local phy regs, e.g: Broadcom switches pseudo-PHY */